Guangqiu Chen

	1996
2		Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154-
	1995
1		Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427

Coauthor Index

1	Hidetoshi Onodera	[1] [2]
2	Keikichi Tamaru	[1] [2]