Hongyu Chen

	2007
23		Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen: Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ASP-DAC 2007: 684-689
22		Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng: Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED 2007: 251-256
21		Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng: Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007)
	2006
20		Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton: Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78
19		Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng: Communication latency aware low power NoC synthesis. DAC 2006: 574-579
18		Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai: Clock Distribution Architectures: A Comparative Study. ISQED 2006: 85-91
	2005
17		Hongyu Chen, Chung-Kuan Cheng: A multi-level transmission line network approach for multi-giga hertz clock distribution. ASP-DAC 2005: 103-106
16		Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris: Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531
15		Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai: A sliding window scheme for accurate clock mesh analysis. ICCAD 2005: 939-946
14		Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng: Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. ICCD 2005: 111-118
13		Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris: Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. ICCD 2005: 497-502
12		Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris: Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199
11		Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 588-599 (2005)
10		Guangrong Yue, Hongyu Chen, Shaoqian Li: Ultra Wideband Time Hopping Impulse Radio Signal Impact on Performance of TD-SCDMA. IEICE Transactions 88-A(9): 2373-2380 (2005)
	2004
9		Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng: A multiple level network approach for clock skew minimization with process variations. ASP-DAC 2004: 263-268
8		Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang: Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449
	2003
7		Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu: An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799
6		Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao: The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20
5		Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang: Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76
4		Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham: Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003)
	2002
3		Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng: Physical Planning Of On-Chip Interconnect Architectures. ICCD 2002: 30-35
2		Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng: Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP 2002: 85-89
	2001
1		Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham: Revisiting floorplan representations. ISPD 2001: 138-143

Coauthor Index

1	Chung-Kuan Cheng	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [14] [16] [17] [19] [20] [21] [22] [23]
2	Andrew A. Chien	[14]
3	Nan-Chi Chou	[7] [12] [16] [21]
4	Truman Collins	[16] [21]
5	Ronald L. Graham	[1] [4] [19]
6	Kevin Hamilton	[22]
7	David M. Harris	[13]
8	Yuanfang Hu	[14] [19]
9	Michael Hutton (Michael D. Hutton, Mike Hutton)	[16] [20] [21]
10	Andrew B. Kahng	[5] [6] [7] [8] [11]
11	Shaoqian Li	[10]
12	Lung-Tien Liu	[12]
13	John F. MacDonald	[7]
14	Ion I. Mandoiu	[5] [6] [11]
15	Takashi Miyoshi	[18]
16	Makoto Mori	[8] [9]
17	Rajeev Murgai	[15] [18]
18	Hoa-van Nguyen	[15] [18]
19	Changge Qiao	[2]
20	Subodh M. Reddy	[15] [18]
21	Rui Shi	[13] [23]
22	Sridhar Srinivasan	[16] [21]
23	Peter Suaris (Peter Ramyalal Suaris)	[7] [12] [16] [21]
24	William W. Walker	[15] [18]
25	Qinke Wang	[5] [6] [8] [11]
26	Gustavo R. Wilke	[15] [18]
27	Bo Yao	[1] [3] [4] [6] [7] [9] [11] [12] [16] [20] [21] [22]
28	Chao-Yang Yeh	[15] [18]
29	Guangrong Yue	[10]
30	Ling Zhang	[22]
31	Feng Zhou	[2] [3]
32	Shuo Zhou	[16] [20] [21]
33	Haikun Zhu	[23]
34	Yi Zhu	[14] [16] [19] [20] [21]
35	Zhengyong Zhu	[7]

Colors in the list of coauthors