 | 2008 |
|---|
| 10 |       | Yi-Hau Chen,
Tzu-Der Chuang,
Yu-Han Chen,
Chen-Han Tsai,
Liang-Gee Chen:
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder.
ISCAS 2008: 29-32 |
| 9 | | Yi-Hau Chen,
Chih-Chi Cheng,
Tzu-Der Chuang,
Ching-Yeh Chen,
Shao-Yi Chien,
Liang-Gee Chen:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Techn. 18(1): 98-109 (2008) |
| 8 | | Yi-Hau Chen,
Shao-Yi Chien,
Ching-Yeh Chen,
Yu-Wen Huang,
Liang-Gee Chen:
Analysis and Hardware Architecture Design of Global Motion Estimation.
Signal Processing Systems 53(3): 285-300 (2008) |
| 7 | | Yi-Hau Chen,
Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC.
Signal Processing Systems 53(3): 335-347 (2008) |
| 2007 |
|---|
| 6 | | Yu-Jen Chen,
Yi-Hau Chen,
Tzu-Der Chuang,
Chung-Te Li,
Shao-Yi Chien,
Liang-Gee Chen:
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension.
SiPS 2007: 515-520 |
| 2006 |
|---|
| 5 | | Yi-Hau Chen,
Ching-Yeh Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
ICME 2006: 365-368 |
| 4 | | Chih-Chi Cheng,
Ching-Yeh Chen,
Yi-Hau Chen,
Liang-Gee Chen:
Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
ISCAS 2006 |
| 3 | | Ching-Yeh Chen,
Yi-Hau Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Frame-level data reuse for motion-compensated temporal filtering.
ISCAS 2006 |
| 2 | | Ching-Yeh Chen,
Chao-Tsung Huang,
Yi-Hau Chen,
Liang-Gee Chen:
Level C+ data reuse scheme for motion estimation with corresponding coding orders.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 553-558 (2006) |
| 2005 |
|---|
| 1 | | Yi-Hau Chen,
Ching-Yeh Chen,
Liang-Gee Chen:
Architecture of global motion compensation for MPEG-4 advanced simple profile.
ISCAS (5) 2005: 1798-1801 |
