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DBLP keys2009
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang: Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. DAC 2009: 87-90
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHai Li, Yiran Chen: An overview of non-volatile memory technology and the implication for tools and architectures. DATE 2009: 731-736
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGuangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li: Tolerating process variations in large, set-associative caches: The buddy cache. TACO 6(2): (2009)
2008
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Xu, Tong Zhang, Yiran Chen: Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. ISCAS 2008: 1898-1901
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov: Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). ISQED 2008: 684-690
2007
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWeng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li: VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Hai Li, Jing Li, Cheng-Kok Koh: Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107
2006
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh: SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163
2005
9no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen: Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDongku Kang, Yiran Chen, Kaushik Roy: Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED 2005: 48-53
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Kaushik Roy, Cheng-Kok Koh: Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. VLSI Syst. 13(1): 75-85 (2005)
2004
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Kaushik Roy, Cheng-Kok Koh: Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
2003
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Kaushik Roy, Cheng-Kok Koh: Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234
2002
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy: Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-937

Coauthor Index

1Venkataramanan Balakrishnan [1] [9] [11]
2Swarup Bhunia [3] [4]
3Dimitar V. Dimitrov [14]
4Xiangyu Dong [16] [18]
5J. Jam [9]
6Dongku Kang [7]
7Cheng-Kok Koh [1] [2] [5] [6] [8] [9] [10] [11] [12] [13] [17]
8Wai-Ching Douglas Lam [9]
9Hai Li [3] [4] [8] [10] [12] [13] [14] [17] [19]
10Helen Li [16]
11Hong Li [11]
12Jian Li [18]
13Jing Li [12]
14Harry Liu [14]
15Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8] [10]
16Guangyu Sun [16] [18]
17T. N. Vijaykumar [3] [4]
18Xiaobin Wang [14] [20]
19Weng-Fai Wong [13] [17]
20Xiaoxia Wu [16]
21Yuan Xie [16] [18]
22Wei Xu [15] [20]
23Tong Zhang [15] [20]

Copyright © Tue Nov 10 20:29:05 2009 by Michael Ley (ley@uni-trier.de)