 | 2009 |
|---|
| 34 |       | Jen-Chieh Liu,
Hong-Yi Huang,
Wei-Bin Yang,
Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop.
DDECS 2009: 186-193 |
| 33 | | Shu-Yu Jiang,
Chan-Wei Huang,
Yu-lung Lo,
Kuo-Hsing Cheng:
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.
IEICE Transactions 92-A(2): 389-400 (2009) |
| 32 | | Yu-lung Lo,
Wei-Bin Yang,
Ting-Sheng Chao,
Kuo-Hsing Cheng:
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer.
IEICE Transactions 92-C(6): 890-893 (2009) |
| 31 | | Kuo-Hsing Cheng,
Yu-Chang Tsai,
Chien-Nan Jimmy Liu,
Kai-Wei Hong,
Chin-Cheng Kuo:
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.
IEICE Transactions 92-C(7): 964-972 (2009) |
| 2008 |
|---|
| 30 | | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chih-Hsien Chang,
Yu-lung Lo,
Wei-Bin Yang,
Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.
DDECS 2008: 64-67 |
| 29 | | Kuo-Hsing Cheng,
Chia-Wei Su,
Hsin-Hsin Ko:
Highly Accurate and Efficient Current-Mode PWM CMOS DC-DC Buck Converter with On-Chip Current-Sensing.
IEICE Transactions 91-C(12): 1941-1950 (2008) |
| 2007 |
|---|
| 28 | | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chia-Wei Su:
A Sub-1V Low-Power High-Speed Static Frequency Divider.
ISCAS 2007: 3848-3851 |
| 2006 |
|---|
| 27 | | Kuo-Hsing Cheng,
Yu-lung Lo:
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs.
DATE Designers' Forum 2006: 178-182 |
| 26 | | Kuo-Hsing Cheng,
Kai-Fei Chang,
Yu-lung Lo,
Ching-Wen Lai,
Yuh-Kuang Tseng:
A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process.
ISCAS 2006 |
| 25 | | Kuo-Hsing Cheng,
Chan-Wei Huang,
Shu-Yu Jiang:
Self-sampled vernier delay line for built-in clock jitter measurement.
ISCAS 2006 |
| 24 | | Kuo-Hsing Cheng,
Shun-Wen Cheng:
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.
J. Inf. Sci. Eng. 22(4): 975-989 (2006) |
| 23 | | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Wen-Shiuan Lee:
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.
Journal of Circuits, Systems, and Computers 15(1): 13-28 (2006) |
| 2005 |
|---|
| 22 | | Kuo-Hsing Cheng,
Chen-Lung Wu,
Yu-lung Lo,
Chia-Wei Su:
A phase-detect synchronous mirror delay for clock skew-compensation circuits.
ISCAS (2) 2005: 1070-1073 |
| 21 | | Kuo-Hsing Cheng,
Shu-Ming Chang,
Shu-Yu Jiang,
Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.
ISCAS (2) 2005: 1174-1177 |
| 20 | | Kuo-Hsing Cheng,
Shun-Wen Cheng:
64-Bit High-Performance Power-Aware Conditional Carry Adder Design.
IEICE Transactions 88-C(6): 1322-1331 (2005) |
| 2004 |
|---|
| 19 |  | Kuo-Hsing Cheng,
Tsung-Shen Chen,
Chia Ming Tu:
A 14-bit, 200 MS/s digital-to-analog converter without trimming.
ISCAS (1) 2004: 353-358 |
| 18 | | Kuo-Hsing Cheng,
Wei-Bin Yang,
Shu-Chang Kuo:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.
ISCAS (1) 2004: 777-780 |
| 17 | | Kuo-Hsing Cheng,
Chia-Hung Wei,
Shu-Yu Jiang:
Static divided word matching line for low-power Content Addressable Memory design.
ISCAS (2) 2004: 629-632 |
| 16 | | Kuo-Hsing Cheng,
Yu-lung Lo:
A fast-lock DLL with power-on reset circuit.
ISCAS (4) 2004: 357-360 |
| 15 | | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.
ISVLSI 2004: 233-236 |
| 14 | | Kuo-Hsing Cheng,
Shun-Wen Cheng,
Chan-Wei Huang:
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.
IWSOC 2004: 65-68 |
| 2003 |
|---|
| 13 | | Kuo-Hsing Cheng,
Yu-lung Lo,
Wen Fang Yu:
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.
ISCAS (2) 2003: 196-199 |
| 12 | | Kuo-Hsing Cheng,
Yang-Han Lee,
Wei-Chun Chang:
A new robust handshake for asymmetric asynchronous micro-pipelines.
ISCAS (5) 2003: 209-212 |
| 11 | | Kuo-Hsing Cheng,
Yung-Hsiang Lin:
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.
ISCAS (5) 2003: 425-428 |
| 10 | | Kuo-Hsing Cheng,
Shu-Yu Jiang,
Zong-Shen Chen:
BIST for clock jitter measurements.
ISCAS (5) 2003: 577-580 |
| 9 | | Kuo-Hsing Cheng,
Chung-Yu Chang,
Chia-Hung Wei:
A CMOS charge pump for sub-2.0 V operation.
ISCAS (5) 2003: 89-92 |
| 8 | | Kuo-Hsing Cheng,
Wei-Chun Chang,
Chia Ming Tu:
A Robust Handshake for Asynchronous System.
IWSOC 2003: 16-19 |
| 7 | | Kuo-Hsing Cheng,
Yu-lung Lo,
Wen Fang Yu,
Shu-Yin Hung:
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.
IWSOC 2003: 90-93 |
| 2002 |
|---|
| 6 | | Kuo-Hsing Cheng,
Shun-Wen Cheng:
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.
VLSI Design 2002: 155-159 |
| 2001 |
|---|
| 5 | | Kuo-Hsing Cheng,
Wei-Bin Yang,
Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL.
ISCAS (4) 2001: 614-617 |
| 4 | | Shun-Wen Cheng,
Kuo-Hsing Cheng:
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning.
ISCAS (5) 2001: 167-170 |
| 1995 |
|---|
| 3 | | Hong-Yi Huang,
Jinn-Shyan Wang,
Yuan-Hua Chu,
Tain-Shun Wu,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS 1995: 1572-1575 |
| 2 | | Chung-Yu Wu,
Jr-Houng Lu,
Kuo-Hsing Cheng:
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
ISCAS 1995: 25-28 |
| 1994 |
|---|
| 1 | | Yuh-Kuang Tseng,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit.
ISCAS 1994: 23-26 |
