 | 2007 |
|---|
| 7 |       | Huy Nam Nguyen,
Vu-Duc Ngo,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
An QoS Aware Mapping of Cores Onto NoC Architectures.
ISPA 2007: 278-288 |
| 6 | | Vu-Duc Ngo,
June-Young Chang,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling.
ISPA 2007: 289-302 |
| 2006 |
|---|
| 5 | | Vu-Duc Ngo,
Huy Nam Nguyen,
Younghwan Bae,
Hanjin Cho,
Hae-Wook Choi:
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.
ISPA Workshops 2006: 791-802 |
| 2004 |
|---|
| 4 |  | David Zier,
Jumnit Hong,
Savithri Venkatachalapathy,
Jarrod Nelson,
John Mark Matson,
Ben Lee,
Younghwan Bae,
Hanjin Cho:
X32V: A Design of Configurable Processor Core for Embedded Systems.
ESA/VLSI 2004: 123-129 |
| 2003 |
|---|
| 3 | | Wonjong Kim,
Seungchul Kim,
Hanjin Cho,
Kwang-youb Lee:
A fast-serial finite field multiplier without increasing the number of registers.
ISCAS (5) 2003: 157-160 |
| 2002 |
|---|
| 2 | | Kibum suh,
Seongmo Park,
Seongmin Kim,
Bontae Koo,
Igkyun Kim,
Kyungsoo Kim,
Hanjin Cho:
An efficient architecture of DCTQ module in MPEG-4 video codec.
ISCAS (1) 2002: 777-780 |
| 2001 |
|---|
| 1 | | Kyungtae Han,
Iksu Eo,
Kyungsu Kim,
Hanjin Cho:
Numerical word-length optimization for CDMA demodulator.
ISCAS (4) 2001: 290-293 |
