 | 2008 |
|---|
| 6 |       | Sejong Oh,
Tag Gon Kim,
Jeonghun Cho,
Elaheh Bozorgzadeh:
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 409-422 (2008) |
| 2007 |
|---|
| 5 | | Jinhwan Kim,
Jeonghun Cho,
Tag Gon Kim:
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures.
IEICE Transactions 90-D(12): 1977-1985 (2007) |
| 2006 |
|---|
| 4 | | Jeonghun Cho,
Yunheung Paek:
Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm.
EUC Workshops 2006: 775-784 |
| 2004 |
|---|
| 3 | | Jeonghun Cho,
Yunheung Paek,
David B. Whalley:
Fast memory bank assignment for fixed-point digital signal processors.
ACM Trans. Design Autom. Electr. Syst. 9(1): 52-74 (2004) |
| 2002 |
|---|
| 2 | | Jeonghun Cho,
Jinhwan Kim,
Yunheung Paek:
A Study on Data Allocation of On-Chip Dual Memory Banks.
Interaction between Compilers and Computer Architectures 2002: 68- |
| 1 | | Jeonghun Cho,
Yunheung Paek,
David B. Whalley:
Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms.
LCTES-SCOPES 2002: 130-138 |
