 | 2009 |
|---|
| 3 |       | Jing-Wun Lin,
Chen-Chieh Wang,
Chin-Yao Chang,
Chung-Ho Chen,
Kuen-Jong Lee,
Yuan-Hua Chu,
Jen-Chieh Yeh,
Ying-Chuan Hsiao:
Full System Simulation and Verification Framework.
IAS 2009: 165-168 |
| 2006 |
|---|
| 2 | | Jinn-Shyan Wang,
Yu-Juey Chang,
Chingwei Yeh,
Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
ISCAS 2006 |
| 1995 |
|---|
| 1 |  | Hong-Yi Huang,
Jinn-Shyan Wang,
Yuan-Hua Chu,
Tain-Shun Wu,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS 1995: 1572-1575 |
