 | 2009 |
|---|
| 62 |       | Yi-Chi Chen,
Hui-Chin Yang,
Chung-Ping Chung,
Wei-Ting Wang:
Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing.
CSE (2) 2009: 31-36 |
| 61 | | Chung-Ping Chung,
Hong-Wei Chen,
Hui-Chin Yang:
Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads.
CSE (2) 2009: 402-407 |
| 60 | | Chih-Chieh Hsiao,
Chung-Ping Chung,
Hui-Chin Yang:
A Hierarchical Primitive Lists Structure for Tile-Based Rendering.
CSE (2) 2009: 408-413 |
| 59 | | Hsiu-ching Hsieh,
Chih-Chieh Hsiao,
Hui-Chin Yang,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Methods for Precise False-Overlap Detection in Tile-Based Rendering.
CSE (2) 2009: 414-419 |
| 58 | | Chung-Ping Chung,
Tung-Lin Lu,
Hui-Chin Yang:
H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method.
CSE (2) 2009: 420-425 |
| 2008 |
|---|
| 57 | | Po-Chun Chang,
I-Wei Wu,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor.
DAC 2008: 776-779 |
| 56 | | I-Wei Wu,
Zhi-Yuan Chen,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Instruction Set Extension Exploration in Multiple-Issue Architecture.
DATE 2008: 764-769 |
| 55 | | Hui-Chin Yang,
Li-Ming Wang,
Chung-Ping Chung:
iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability.
ICYCS 2008: 1309-1313 |
| 54 | | Wei-Hau Chiao,
Chung-Ping Chung:
Filtering of Unnecessary Branch Predictor Lookups for Low-power Processor Architecture.
J. Inf. Sci. Eng. 24(4): 1127-1142 (2008) |
| 2007 |
|---|
| 53 | | Wei-Ting Wang,
Yi-Chi Chen,
Chung-Ping Chung:
A Run-Time Reconfigurable Fabric for 3D Texture Filtering.
ASAP 2007: 180-185 |
| 52 |  | Wei-Ting Wang,
Wai-Hong Tam,
Yi-Chi Chen,
Kuen-Cheng Chiang,
Chung-Ping Chung:
Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing.
ERSA 2007: 99-106 |
| 51 | | I-Wei Wu,
Shih-Chia Huang,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints.
HiPEAC 2007: 291-305 |
| 2006 |
|---|
| 50 | | Hui-Chin Yang,
Chung-Ping Chung:
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability.
CDES 2006: 146-152 |
| 49 | | Bin-Hua Tein,
I-Wei Wu,
Chung-Ping Chung:
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer.
CDES 2006: 91-96 |
| 48 | | Cher-Sheng Cheng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems.
Inf. Process. Manage. 42(2): 407-428 (2006) |
| 47 | | Cher-Sheng Cheng,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems.
Inf. Process. Manage. 42(3): 729-750 (2006) |
| 2005 |
|---|
| 46 | | Wei-Hao Chiao,
Tsung-Hsi Weng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung,
Jimmy Lu:
Low-Power Data Address Bus Encoding Method.
CDES 2005: 204-210 |
| 45 | | Yau-Chong Hu,
Wei-Hau Chiao,
Jean Jyh-Jiun Shann,
Chung-Ping Chung,
Wen-Feng Chen:
Low-Power Branch Prediction.
CDES 2005: 211-217 |
| 44 | | Wann-Yun Shieh,
Chung-Ping Chung:
A statistics-based approach to incrementally update inverted files.
Inf. Process. Manage. 41(2): 275-288 (2005) |
| 43 | | Ching-Wen Chen,
Chung-Ping Chung:
Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving.
The Journal of Supercomputing 34(1): 63-80 (2005) |
| 2004 |
|---|
| 42 | | Cher-Sheng Cheng,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems.
ITCC (2) 2004: 229-235 |
| 41 | | Yung-Cheng Ma,
Tien-Fu Chen,
Chung-Ping Chung:
Branch-and-bound task allocation with task clustering-based pruning.
J. Parallel Distrib. Comput. 64(11): 1223-1240 (2004) |
| 40 | | Kelvin Lin,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Code compression by register operand dependency.
Journal of Systems and Software 72(3): 295-304 (2004) |
| 39 | | Lee-Ren Ton,
Lung-Chung Chang,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
A software/hardware cooperated stack operations folding model for Java processors.
Journal of Systems and Software 72(3): 377-387 (2004) |
| 2003 |
|---|
| 38 | | Wann-Yun Shieh,
Chung-Ping Chung:
A Statistics-Based Approach to Incrementally Update Inverted Files.
IKE 2003: 38-43 |
| 37 | | Wann-Yun Shieh,
Tien-Fu Chen,
Chung-Ping Chung:
A Tree-Based inverted File for Fast Ranked-Document Retrieval.
IKE 2003: 64-69 |
| 36 | | Kelvin Lin,
Chung-Ping Chung,
Jean Jyh-Jiun Shann:
Compressing MIPS code by multiple operand dependencies.
ACM Trans. Embedded Comput. Syst. 2(4): 482-508 (2003) |
| 35 | | Wann-Yun Shieh,
Tien-Fu Chen,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Inverted file compression through document identifier reassignment.
Inf. Process. Manage. 39(1): 117-131 (2003) |
| 34 | | Wann-Yun Shieh,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
An Inverted File Cache for Fast Information Retrieval.
J. Inf. Sci. Eng. 19(4): 681-695 (2003) |
| 33 | | Ching-Wen Chen,
Neng-Pin Lu,
Chung-Ping Chung:
3-Disjoint gamma interconnection networks.
Journal of Systems and Software 66(2): 129-134 (2003) |
| 32 | | Yung-Cheng Ma,
Jih-Ching Chiu,
Tien-Fu Chen,
Chung-Ping Chung:
Variable-size data item placement for load and storage balancing.
Journal of Systems and Software 66(2): 157-166 (2003) |
| 2002 |
|---|
| 31 | | Kelvin Lin,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Code Compression by Register Operand Dependency.
Interaction between Compilers and Computer Architectures 2002: 91-101 |
| 30 | | Jih-Ching Chiu,
Michael Jin-Yi Wang,
Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.
J. Inf. Sci. Eng. 18(3): 393-409 (2002) |
| 29 | | Jih-Ching Chiu,
Michael Jin-Yi Wang,
Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture.
J. Inf. Sci. Eng. 18(3): 393-409 (2002) |
| 28 | | Lee-Ren Ton,
Lung-Chung Chang,
Chung-Ping Chung:
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes.
Journal of Systems Architecture 48(1-3): 1-16 (2002) |
| 27 | | Yung-Cheng Ma,
Tien-Fu Chen,
Chung-Ping Chung:
Posting file partitioning and parallel information retrieval.
Journal of Systems and Software 63(2): 113-127 (2002) |
| 26 | | Lee-Ren Ton,
Lung-Chung Chang,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Design of an optimal folding mechanism for Java processors.
Microprocessors and Microsystems 26(8): 341-352 (2002) |
| 2001 |
|---|
| 25 | | Ching-Wen Chen,
Chung-Ping Chung:
Fault-tolerant gamma interconnection network without backtracking.
Journal of Systems and Software 58(1): 23-31 (2001) |
| 24 | | Yung-Cheng Ma,
Chung-Ping Chung:
A dominance relation enhanced branch-and-bound task allocation.
Journal of Systems and Software 58(2): 125-134 (2001) |
| 2000 |
|---|
| 23 | | Lee-Ren Ton,
Lung-Chung Chang,
Chung-Ping Chung:
Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note).
Euro-Par 2000: 994-997 |
| 22 | | Jih-Ching Chiu,
I-Huan Huang,
Chung-Ping Chung:
Design of Instruction Stream Buffer with Trace Support for X86 Processors.
ICCD 2000: 294-299 |
| 21 | | R.-Ming Shiu,
Neng-Pin Lu,
Chung-Ping Chung:
Applying stack simulation for branch target buffers.
Journal of Systems and Software 52(1): 67-78 (2000) |
| 1999 |
|---|
| 20 | | Ruey-Liang Ma,
Chung-Ping Chung:
Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System.
J. Inf. Sci. Eng. 15(6): 859-884 (1999) |
| 1997 |
|---|
| 19 | | Lee-Ren Ton,
Lung-Chung Chang,
Min-Fu Kao,
Han-Min Tseng,
Shi-Sheng Shang,
Ruey-Liang Ma,
Dze-Chaung Wang,
Chung-Ping Chung:
Instruction Folding in Java Processor.
ICPADS 1997: 138-143 |
| 18 | | Shyh-An Chi,
R.-Ming Shiu,
Jih-Ching Chiu,
Si-En Chang,
Chung-Ping Chung:
Instruction Cache Prefetching with Extended BTB.
ICPADS 1997: 360- |
| 1996 |
|---|
| 17 | | Chang-Chung Liu,
R.-Ming Shiu,
Chung-Ping Chung:
Register renaming for x86 superscalar design.
ICPADS 1996: 336-343 |
| 16 | | Neng-Pin Lu,
Chung-Ping Chung:
A Fault-Tolerant Multistage Combining Network.
J. Parallel Distrib. Comput. 34(1): 14-28 (1996) |
| 1995 |
|---|
| 15 | | Ruey-Liang Ma,
Chung-Ping Chung:
Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog.
Comput. J. 38(6): 457-470 (1995) |
| 14 | | Hong Chich Chou,
Chung-Ping Chung:
An Optimal Instruction Scheduler for Superscalar Processor.
IEEE Trans. Parallel Distrib. Syst. 6(3): 303-313 (1995) |
| 13 | | Ren-Lianq Cheng,
Chung-Ping Chung:
An Approximate Agreement Algorithm for Wraparound Meshes.
International Journal of High Speed Computing 7(3): 407-419 (1995) |
| 12 | | Neng-Pin Lu,
Chung-Ping Chung:
Memory System Design in Superscalar Processing.
International Journal of High Speed Computing 7(3): 421-443 (1995) |
| 1994 |
|---|
| 11 | | Ruey-Liang Ma,
Chung-Ping Chung:
Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog.
ICPADS 1994: 744-751 |
| 10 | | Hong Chich Chou,
Chung-Ping Chung:
Optimal multiprocessor task scheduling using dominance and equivalence relations.
Computers & OR 21(4): 463-475 (1994) |
| 9 | | Yuh-Horng Shiau,
Chung-Ping Chung:
Effects and Handling of Instruction Class Contention in Superscalar Processing.
International Journal of High Speed Computing 6(3): 357-373 (1994) |
| 1993 |
|---|
| 8 | | Hong Chich Chou,
Chung-Ping Chung:
Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm.
BIT 33(3): 354-371 (1993) |
| 7 | | Ren-Lianq Cheng,
Chung-Ping Chung:
Reaching Approximate Agreement on Hypercube.
Parallel Computing 19(7): 765-775 (1993) |
| 1992 |
|---|
| 6 | | Chung-Ping Chung,
Wen-Yang Lin:
Vectorization of Sorting Algorithms.
International Journal of High Speed Computing 4(3): 213-232 (1992) |
| 5 | | Hong Chich Chou,
Chung-Ping Chung:
Upper Bound Analysis of Scheduling Arbitrary-Delay Instructions on Typed Pipelined Processors.
International Journal of High Speed Computing 4(4): 301-312 (1992) |
| 4 | | Hong Chich Chou,
Chung-Ping Chung:
A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle.
Parallel Computing 18(4): 393-399 (1992) |
| 3 | | Yuh-Horng Shiau,
Chung-Ping Chung:
Adoptability and effectiveness of microcode compaction algorithms in superscalar processing.
Parallel Computing 18(5): 497-510 (1992) |
| 1991 |
|---|
| 2 | | Cheng Chen,
Chung-Ping Chung,
Cheng-Chin Chiang,
Hsin-Chia Fu,
S. J. Wang:
An Or-Parallel Inference Model Based on Multi RISC-Style Processing System.
J. Inf. Sci. Eng. 7(4): 487-512 (1991) |
| 1989 |
|---|
| 1 | | Chung-Ping Chung,
Shyi-Chyi Jeng,
Hong Chich Chou,
Cheng Chen:
Design of Dual-ALU CRISC and Its Concurrent Execution .
J. Inf. Sci. Eng. 5(3): 251-274 (1989) |
