Maciej J. Ciesielski

	2009
44		D. Gomez-Prado, Q. Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon: Optimizing data flow graphs to minimize hardware implementation. DATE 2009: 117-122
	2008
43		Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang: A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427
42		Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491
	2007
41		Maciej J. Ciesielski, Serkan Askar, D. Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon: Data-flow transformations using Taylor expansion diagrams. DATE 2007: 455-460
	2006
40		Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar: Efficient factorization of DSP transforms using taylor expansion diagrams. DATE 2006: 754-755
39		Maciej J. Ciesielski, Priyank Kalla, Serkan Askar: Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. IEEE Trans. Computers 55(9): 1188-1201 (2006)
	2005
38		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20
37		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: Yield-aware Floorplanning. DSD 2005: 247-253
36		Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski: Functional test generation based on word-level SAT. Journal of Systems Architecture 51(8): 488-511 (2005)
	2004
35		Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski: A new state assignment technique for testing and low power. DAC 2004: 510-513
34		Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
	2003
33		Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129
	2002
32		Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-291
31		Maciej J. Ciesielski, Serkan Askar, Samuel Levitin: Analytical approach to layout generation of datapath cells. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1480-1488 (2002)
30		Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicitstate enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 810-826 (2002)
29		Congguang Yang, Maciej J. Ciesielski: BDS: a BDD-based logic optimization system. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 866-876 (2002)
	2001
28		Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski: LPSAT: a unified approach to RTL satisfiability. DATE 2001: 398-402
27		Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
26		Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski: Strategies for solving the Boolean satisfiability problem using binary decision diagrams. Journal of Systems Architecture 47(6): 491-503 (2001)
	2000
25		Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDS: a BDD-based logic optimization system. DAC 2000: 92-97
24		Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. DATE 2000: 232-236
23		Congguang Yang, Maciej J. Ciesielski: Synthesis for Mixed CMOS/PTl Logic. DATE 2000: 750
22		Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski: Retiming-based factorization for sequential logic optimization. ACM Trans. Design Autom. Electr. Syst. 5(3): 373-398 (2000)
	1999
21		Priyank Kalla, Maciej J. Ciesielski: Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. DATE 1999: 638-642
20		Serkan Askar, Maciej J. Ciesielski: Analytical approach to custom datapath design. ICCAD 1999: 98-101
19		Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal: BDD Decomposition for Efficient Logic Synthesis. ICCD 1999: 626-
18		Durgam Vahia, Maciej J. Ciesielski: Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163
	1998
17		Balakrishnan Iyer, Maciej J. Ciesielski: Reencoding for cycle-time minimization under fixed encoding length. ICCAD 1998: 312-315
16		Priyank Kalla, Maciej J. Ciesielski: A comprehensive approach to the partial scan problem using implicit state enumeration. ITC 1998: 651-657
15		Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu: Wave-pipelining: a tutorial and research survey. IEEE Trans. VLSI Syst. 6(3): 464-474 (1998)
	1997
14		Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga: Intelligent Simulation for Computer Aided Design of Optical Networks. ONDM 1997: 73-86
13		Priyank Kalla, Maciej J. Ciesielski: Testability of Sequential Circuits with Multi-Cycle False Path. VTS 1997: 322-328
	1996
12		Balakrishnan Iyer, Maciej J. Ciesielski: Metamorphosis: state assignment by retiming and re-encoding. ICCAD 1996: 614-617
	1994
11		Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski: Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166
	1993
10		Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)
	1992
9		Maya K. Yajnik, Maciej J. Ciesielski: Finite State Machine Decomposition Using Multiway Partitioning. ICCD 1992: 320-323
8		Zafar Hasan, David Harrison, Maciej J. Ciesielski: A Fast Partitioning Method for PLA-Based FPGAs. IEEE Design & Test of Computers 9(4): 34-39 (1992)
7		Maciej J. Ciesielski, Seiyang Yang: PLADE: a two-stage PLA decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 943-954 (1992)
	1991
6		Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio: A Unified Approach to Input-Output Encoding for FSM State Assignment. DAC 1991: 176-181
5		Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643
4		Seiyang Yang, Maciej J. Ciesielski: Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 4-12 (1991)
	1989
3		Maciej J. Ciesielski: Layer assignment for VLSI interconnect delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 702-707 (1989)
	1987
2		Maciej J. Ciesielski, E. Kinnen: Digraph Relaxation for 2-Dimensional Placement of IC Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 55-66 (1987)
	1985
1		Maciej J. Ciesielski: Two-Dimensional Routing for the Silc Silicon Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 198-203 (1985)

Coauthor Index

1	Serkan Askar	[20] [31] [39] [40] [41]
2	Hyuncheol Baik	[43]
3	Surendra Bommu	[22]
4	Emmanuel Boutillon	[40] [41] [44]
5	Wayne P. Burleson (Wayne Burleson)	[11] [15]
6	Imrich Chlamtac	[14]
7	Sangwook Cho	[35]
8	Youngrae Cho	[43]
9	Kyumyung Choi	[43]
10	L. W. Cotten	[11]
11	Marc Davio	[6]
12	Rolf Drechsler	[34]
13	Görschwin Fey	[34]
14	Andrea Fumagalli	[14]
15	D. Gomez-Prado	[40] [41] [44]
16	Jérémie Guillot	[40] [41] [44]
17	Ian G. Harris	[33]
18	David Harrison	[8]
19	Zafar Hasan	[8]
20	ChiLai Huang	[24]
21	Balakrishnan Iyer	[12] [17]
22	Donald A. Joy	[5] [10]
23	Priyank Kalla	[13] [16] [21] [24] [26] [28] [30] [32] [39]
24	Dusung Kim	[43]
25	Jaebum Kim	[43]
26	Kyungkuk Kim	[43]
27	Namdo Kim	[43]
28	E. Kinnen	[2]
29	Fabian Klass	[11] [15]
30	Israel Koren	[37] [38]
31	Samuel Levitin	[31]
32	W. Liu	[15]
33	Byeongun Min	[43]
34	Niall O'Neill	[22]
35	Sungju Park	[35]
36	Q. Ren	[40] [44]
37	Bruno Rouzeyre	[27] [32]
38	Chester A. Ruszczyk	[14]
39	Jia-Jye Shen	[6]
40	Kyuho Shim	[42] [43]
41	Vigyan Singhal	[19] [25]
42	Kesava R. Talupuru	[36] [42]
43	Durgam Vahia	[18]
44	Gosse Wedzinga	[14]
45	Zhaojun Wo	[37] [38]
46	Maya K. Yajnik	[9]
47	Congguang Yang	[19] [23] [25] [29]
48	Seiyang Yang	[4] [7] [35] [42] [43]
49	Zhihong Zeng	[24] [26] [27] [28] [32] [33] [36]
50	Qiushuang Zhang	[33]

Colors in the list of coauthors