José Manuel Colmenar Coauthor index DBLP Vis pubzone.org

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DBLP keys2009
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Characterizing asynchronous variable latencies through probability distribution functions. Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 483-497 (2009)
2008
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo: Modelling Asynchronous Systems using Probability Distribution Functions. PDP 2008: 3-11
2006
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. DSD 2006: 423-432
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGuadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: A Power-Aware Technique for Functional Units in High-Performance Processors. DSD 2006: 456-459
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López: Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. Euro-Par 2006: 495-505
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGuadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López: A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. PATMOS 2006: 514-523
2005
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGuadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar: Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. PATMOS 2005: 40-48
2004
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSonia López, Oscar Garnica, José Manuel Colmenar: Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. PATMOS 2004: 623-632
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida: Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119

Coauthor Index

1Oscar Garnica [1] [2] [3] [4] [5] [6] [7] [8] [9]
2Román Hermida [1]
3José Ignacio Hidalgo [1] [3] [4] [5] [6] [7] [8] [9]
4Juan Lanchares [1] [3] [4] [5] [6] [7] [8] [9]
5Sonia López [1] [2] [4] [5] [7]
6Guadalupe Miñana [3] [4] [5] [6] [7]
7Noelia Morón [8]

Copyright © Mon Nov 30 15:58:31 2009 by Michael Ley (ley@uni-trier.de)