Zhiqiang Cui

	2008
7		Zhiqiang Cui, Zhongfeng Wang: Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462
	2007
6		Zhiqiang Cui, Zhongfeng Wang: Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920
5		Zhiqiang Cui, Zhongfeng Wang: Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS 2007: 216-221
4		Zhongfeng Wang, Zhiqiang Cui: Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(1): 104-114 (2007)
3		Zhongfeng Wang, Zhiqiang Cui: A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(4): 483-488 (2007)
	2006
2		Zhiqiang Cui, Zhongfeng Wang: A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006
1		Zhiqiang Cui, Zhongfeng Wang: Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006

Coauthor Index

1

Zhongfeng Wang

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