Jean-Luc Danger

	2009
17		Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar: Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645
	2008
16		Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98
15		Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125
14		Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger: Practical Setup Time Violation Attacks on AES. EDCC 2008: 91-96
13		Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet: Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17
12		Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley: Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257
11		Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst: Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166
10		Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32
9		Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger: Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18
8		Sami Mekki, Jean-Luc Danger, Benoit Miscopein, Jean Schwoerer, Joseph Jean Boutros: Probabilistic Equalizer for Ultra-Wideband Energy Detection. VTC Spring 2008: 1108-1112
7		Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR abs/0809.3942: (2008)
	2007
6		Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley: Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL 2007: 665-669
5		Qing Xu, M. B. C. Silva, Jean-Luc Danger, Sylvain Guilley, Patrick Bellot, Philippe Gallion, Francisco Mendieta: Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference. RIVF 2007: 158-165
4		F. Guilloud, E. Boutillon, Jacky Tousch, Jean-Luc Danger: Generic Description and Synthesis of LDPC Decoders. IEEE Transactions on Communications 55(11): 2084-2091 (2007)
	2000
3		Andrés D. García, Jean-Luc Danger, Wayne P. Burleson: Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220
	1999
2		L. Naviner, Jean-Luc Danger, C. Laurent: High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA. FPGA 1999: 249
1		Andrés D. García, Wayne P. Burleson, Jean-Luc Danger: Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404

Coauthor Index

1	Patrick Bellot	[5]
2	Taha Beyrouthy	[7] [16]
3	E. Boutillon	[4]
4	Joseph Jean Boutros (Joseph Boutros)	[8]
5	Wayne P. Burleson (Wayne Burleson)	[1] [3]
6	Sumanta Chaudhuri	[6] [7] [9] [10] [12] [15] [16]
7	Laurent Fesquet	[7] [16]
8	Florent Flament	[15]
9	Philippe Gallion	[5]
10	Andrés D. García	[1] [3]
11	Tarik Graba	[10]
12	Sylvain Guilley	[5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16] [17]
13	F. Guilloud	[4]
14	Philippe Hoogvorst	[7] [9] [10] [11] [12] [15] [16]
15	C. Laurent	[2]
16	Yves Mathieu	[17]
17	Sami Mekki	[8]
18	Francisco Mendieta	[5]
19	Benoit Miscopein	[8]
20	Maxime Nassar	[10] [17]
21	L. Naviner	[2]
22	Renaud Pacalet	[13]
23	Alin Razafindraibe	[16]
24	Marc Renaudin	[16]
25	Laurent Sauvage	[10] [11] [13] [17]
26	Jean Schwoerer	[8]
27	Nidhal Selmane	[13] [14]
28	M. B. C. Silva	[5]
29	Jacky Tousch	[4]
30	Vinh-Nga Vong	[10]
31	Qing Xu	[5]

Colors in the list of coauthors