 | 2009 |
|---|
| 7 |       | Shidhartha Das,
David Blaauw,
David Bull,
Krisztián Flautner,
Rob Aitken:
Addressing design margins through error-tolerant circuits.
DAC 2009: 11-12 |
| 2008 |
|---|
| 6 | | Ganesh S. Dasika,
Shidhartha Das,
Kevin Fan,
Scott A. Mahlke,
David Bull:
DVFS in loop accelerators using BLADES.
DAC 2008: 894-897 |
| 2004 |
|---|
| 5 | | Seokwoo Lee,
Shidhartha Das,
Valeria Bertacco,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge:
Circuit-aware architectural simulation.
DAC 2004: 305-310 |
| 4 | | Seokwoo Lee,
Shidhartha Das,
Toan Pham,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge:
Reducing pipeline energy demands with local DVS and dynamic retiming.
ISLPED 2004: 319-324 |
| 3 | | Dan Ernst,
Shidhartha Das,
Seokwoo Lee,
David Blaauw,
Todd M. Austin,
Trevor N. Mudge,
Nam Sung Kim,
Krisztián Flautner:
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
IEEE Micro 24(6): 10-20 (2004) |
| 2003 |
|---|
| 2 | | Shidhartha Das,
Kanak Agarwal,
David Blaauw,
Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections.
ICCD 2003: 264- |
| 1 | | Dan Ernst,
Nam Sung Kim,
Shidhartha Das,
Sanjay Pant,
Rajeev R. Rao,
Toan Pham,
Conrad H. Ziesler,
David Blaauw,
Todd M. Austin,
Krisztián Flautner,
Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
MICRO 2003: 7-18 |
