K. De

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1997

3 K. De: Test methodology for embedded cores which protects intellectual property. VTS 1997: 2-9

1994

2 K. De, C. Natarajan, D. Nair, P. Banerjee: RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2): 186-195 (1994)

1993

1 K. De, P. Banerjee: PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. VLSI Syst. 1(4): 514-525 (1993)

	1997
3		K. De: Test methodology for embedded cores which protects intellectual property. VTS 1997: 2-9
	1994
2		K. De, C. Natarajan, D. Nair, P. Banerjee: RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2): 186-195 (1994)
	1993
1		K. De, P. Banerjee: PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. VLSI Syst. 1(4): 514-525 (1993)

Coauthor Index

1 P. Banerjee [1] [2]

2 D. Nair [2]

3 C. Natarajan [2]