| 2009 | ||
|---|---|---|
| 62 | Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar: Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 | |
| 2008 | ||
| 61 | Hamed F. Dadgour, Vivek De, Kaustav Banerjee: Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD 2008: 270-277 | |
| 60 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 | |
| 2007 | ||
| 59 | Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De: Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 | |
| 58 | Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. VLSI Syst. 15(7): 746-757 (2007) | |
| 2006 | ||
| 57 | Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De: Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006 | |
| 56 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the data switching activity of serialized datastreams. ISCAS 2006 | |
| 55 | Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De: Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 | |
| 54 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432 | |
| 53 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak: Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612 | |
| 52 | Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin: Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) | |
| 51 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006) | |
| 2005 | ||
| 50 | Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-aware low-power design with voltage scaling. DAC 2005: 529-534 | |
| 49 | James Tschanz, Keith A. Bowman, Vivek De: Variation-tolerant circuits: circuit solutions and techniques. DAC 2005: 762-763 | |
| 48 | Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge: Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD 2005: 535-540 | |
| 47 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 | |
| 46 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De: A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD 2005: 567-573 | |
| 45 | Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra: Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467 | |
| 44 | Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De: Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 | |
| 43 | James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De: Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. ISCAS (1) 2005: 9-12 | |
| 42 | Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De: Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ISLPED 2005: 26-29 | |
| 41 | Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra: Monolithic voltage conversion in low-voltage CMOS technologies. Microelectronics Journal 36(9): 863-867 (2005) | |
| 2004 | ||
| 40 | Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De: Design optimizations for microprocessors at low temperature. DAC 2004: 2-5 | |
| 39 | Shekhar Borkar, Tanay Karnik, Vivek De: Design and reliability challenges in nanometer technologies. DAC 2004: 75 | |
| 38 | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De: Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED 2004: 263-268 | |
| 37 | Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521 | |
| 2003 | ||
| 36 | Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De: Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 | |
| 35 | Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De: Compiler Support for Reducing Leakage Energy Consumption. DATE 2003: 11146-11147 | |
| 34 | Stephen Tang, Siva Narendra, Vivek De: Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. ISLPED 2003: 199-204 | |
| 33 | Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279- | |
| 32 | Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman: Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. VLSI Syst. 11(3): 514-522 (2003) | |
| 31 | Vivek De, Luca Benini: Guest editorial. IEEE Trans. VLSI Syst. 11(5): 753-754 (2003) | |
| 30 | Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. VLSI Syst. 11(5): 863-870 (2003) | |
| 2002 | ||
| 29 | Kanad Ghose, Patrick H. Madden, Vivek De, Peter M. Kogge: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002 ACM 2002 | |
| 28 | Vivek De, Mary Jane Irwin, Ingrid Verbauwhede, Christian Piguet: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002 ACM 2002 | |
| 27 | Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 | |
| 26 | George Sery, Shekhar Borkar, Vivek De: Life is CMOS: why chase the life after? DAC 2002: 78-83 | |
| 25 | Tanay Karnik, Shekhar Borkar, Vivek De: Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 | |
| 24 | Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan: Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED 2002: 19-23 | |
| 23 | Vivek De: Leakage-tolerant design techniques for high performance processors. ISPD 2002: 28-28 | |
| 22 | Ron Wilson, Siva Narendra, Vivek De: Evening Panel Discussion: Process Variation: Is It Too Much to Handle? ISQED 2002: 213- | |
| 21 | Jaume Segura, Vivek De, Ali Keshavarzi: Challenges in Nanometric Technology Scaling: Trends and Projections. VTS 2002: 447-448 | |
| 20 | Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins: Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Design & Test of Computers 19(5): 36-43 (2002) | |
| 19 | Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De: Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. VLSI Syst. 10(2): 91-95 (2002) | |
| 2001 | ||
| 18 | Enrico Macii, Vivek De, Mary Jane Irwin: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001 ACM 2001 | |
| 17 | James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De: Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 | |
| 16 | Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar: Scaling of stack effect and its application for leakage reduction. ISLPED 2001: 195-200 | |
| 15 | Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De: Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED 2001: 207-212 | |
| 2000 | ||
| 14 | Vivek De, Shekhar Borkar: Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI 2000: 1-6 | |
| 13 | Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De: Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243 | |
| 12 | Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De: Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC 2000: 1051-1059 | |
| 11 | Liqiong Wei, Kaushik Roy, Vivek De: Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design 2000: 24-29 | |
| 1999 | ||
| 10 | Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435 | |
| 9 | Vivek De, Shekhar Borkar: Technology and design challenges for low power and high performance. ISLPED 1999: 163-168 | |
| 8 | Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 | |
| 7 | Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. VLSI Syst. 7(1): 16-24 (1999) | |
| 1998 | ||
| 6 | Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494 | |
| 1997 | ||
| 5 | Pankaj Pant, Vivek De, Abhijit Chatterjee: Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. DAC 1997: 403-408 | |
| 4 | Xinghai Tang, Vivek De, James D. Meindl: Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. VLSI Syst. 5(4): 369-376 (1997) | |
| 1996 | ||
| 3 | Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl: Circuit techniques for low-power CMOS GSI. ISLPED 1996: 193-196 | |
| 2 | Xinghai Tang, Vivek De, James D. Meindl: Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED 1996: 233-236 | |
| 1 | Vivek De, James D. Meindl: A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED 1996: 371-375 | |