Vijay Degalahal

	2009
12		Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embedded Comput. Syst. 8(4): (2009)
	2007
11		Taylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal: Compiler-Directed Code Restructuring for Operating with Compressed Arrays. VLSI Design 2007: 221-226
10		Mahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal: Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. VLSI Design 2007: 227-232
	2006
9		Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664
	2005
8		Vijay Degalahal, Tim Tuan: Methodology for high level estimation of FPGA power consumption. ASP-DAC 2005: 657-660
7		Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-Directed Instruction Duplication for Soft Error Detection. DATE 2005: 1056-1057
6		Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft errors issues in low-power caches. IEEE Trans. VLSI Syst. 13(10): 1157-1166 (2005)
	2004
5		Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft error and energy consumption interactions: a data cache perspective. ISLPED 2004: 132-137
4		Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508
3		Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing instruction cache energy consumption using a compiler-based strategy. TACO 1(1): 3-33 (2004)
	2003
2		Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing Soft Errors in Leakage Optimized SRAM Design. VLSI Design 2003: 227-233
	2002
1		Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-directed instruction cache leakage optimization. MICRO 2002: 208-218

Coauthor Index

1	Guangyu Chen	[11]
2	Chita R. Das	[9]
3	Jie S. Hu	[1] [3] [7] [12]
4	Mary Jane Irwin	[1] [2] [3] [4] [5] [6] [7] [12]
5	Mahmut T. Kandemir	[1] [3] [5] [6] [7] [10] [11] [12]
6	Feihui Li	[7] [12]
7	Lin Li	[5] [6]
8	Chrysostomos Nicopoulos	[9]
9	Ozcan Ozturk	[10] [11]
10	Dongkook Park	[9]
11	R. Ramanarayanan	[4]
12	Thomas D. Richardson	[9]
13	Tim Tuan	[8]
14	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[1] [2] [3] [4] [5] [6] [7] [9] [12]
15	Yuan Xie	[4] [9]
16	Taylan Yemliha	[11]
17	Wei Zhang	[1] [3]