José G. Delgado-Frias

	2009
55		Kylan Robinson, José G. Delgado-Frias: Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures. ERSA 2009: 275-278
54		Ruirui Guo, José G. Delgado-Frias: IP Routing table compaction and sampling schemes to enhance TCAM cache performance. Journal of Systems Architecture - Embedded Systems Design 55(1): 61-69 (2009)
	2008
53		Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi: FPGA Schemes with Optimized Routing for the Advanced Encryption Standard. ERSA 2008: 311-312
52		Michael A. Turi, José G. Delgado-Frias: High-performance low-power AND and Sense-Amp address decoders with selective precharging. ISCAS 2008: 1464-1467
51		Mitchell J. Myjak, José G. Delgado-Frias: A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. IEEE Trans. VLSI Syst. 16(1): 14-23 (2008)
	2007
50		H. Lui, José G. Delgado-Frias, Sirisha Medidi: Using a two-timer scheme to detect selfish nodes in mobile ad-hoc networks. Communications, Internet, and Information Technology 2007: 181-186
49		R. Guo, José G. Delgado-Frias: A novel compaction scheme for routing tables in TCAM to enhance cache hit rate. Communications, Internet, and Information Technology 2007: 210-215
48		H. Lin, José G. Delgado-Frias, Sirisha Medidi: Using a cache scheme to detect selfish nodes in mobile ad hoc networks. Communications, Internet, and Information Technology 2007: 61-66
47		Rongsen He, José G. Delgado-Frias: Redundant Array of Independent Fabrics - An Architecture for Next Generation Network. GLOBECOM 2007: 2763-2768
46		Li Zhao, José G. Delgado-Frias: MARS: Misbehavior Detection in Ad Hoc Networks. GLOBECOM 2007: 941-945
45		Daniel R. Blum, José G. Delgado-Frias: Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. ISCAS 2007: 2786-2789
44		Rongsen He, José G. Delgado-Frias: Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers. IEEE Trans. Parallel Distrib. Syst. 18(12): 1727-1739 (2007)
43		Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru: Preface. Integration 40(2): 61 (2007)
	2006
42		Rongsen He, José G. Delgado-Frias: Interleaved Multistage Switching Fabrics for Scalable High Performance Routers. GLOBECOM 2006
41		Suryanarayana Tatapudi, José G. Delgado-Frias: A mesochronous pipeline scheme for high performance low power digital systems. ISCAS 2006
40		Mitchell J. Myjak, José G. Delgado-Frias: Superpipelined reconfigurable hardware for DSP. ISCAS 2006
39		Li Zhao, José G. Delgado-Frias: On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks. Wireless and Optical Communications 2006
	2005
38		Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias: Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
37		Mitchell J. Myjak, José G. Delgado-Frias: A Symmetric Differential Clock Generator for Bit-Serial Hardware. CDES 2005: 159-164
36		Suryanarayana Tatapudi, José G. Delgado-Frias: A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme. CDES 2005: 191-197
35		Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias: Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. CDES 2005: 28-34
34		Jin Liu, José G. Delgado-Frias: DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip. CDES 2005: 97-103
33		Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A distributed FIFO scheme for on chip communication. ISCAS (2) 2005: 1851-1854
32		Suryanarayana Tatapudi, José G. Delgado-Frias: A High Performance Hybrid Wave-Pipelined Multiplier. ISVLSI 2005: 282-283
	2004
31		Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias: H-Tree Interconnection Structure for Reconfigurable DSP Hardware. ERSA 2004: 170-176
30		Andy Widjaja, José G. Delgado-Frias: An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware. ESA/VLSI 2004: 530-535
29		Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias: A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI 2004: 536-540
28		Mitchell J. Myjak, José G. Delgado-Frias: Pipelined Multipliers for Reconfigurable Hardware. IPDPS 2004
	2003
27		Mitchell J. Myjak, José G. Delgado-Frias: A Two-Level Reconfigurable Architecture for Digital Signal Processing. VLSI 2003: 21-27
26		Fred L. Anderson IV, José G. Delgado-Frias: A Reconfigurable Switch for a DSP Array. VLSI 2003: 3-6
25		Daniel R. Blum, José G. Delgado-Frias: A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. VLSI 2003: 58-64
	2001
24		José G. Delgado-Frias, Girish B. Ratanpal: A VLSI wrapped wave front arbiter for crossbar switches. ACM Great Lakes Symposium on VLSI 2001: 85-88
23		Victor A. Skormin, José G. Delgado-Frias, Dennis L. McGee, Joseph Giordano, Leonard J. Popyack, Vladimir I. Gorodetski, Alexander O. Tarakanov: BASIS: A Biological Approach to System Information Security. MMM-ACNS 2001: 127-142
	2000
22		José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan: A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70
	1999
21		Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A neuro-emulator with embedded capabilities for generalized learning. Journal of Systems Architecture 45(14): 1219-1243 (1999)
	1998
20		Douglas H. Summerville, José G. Delgado-Frias: Approaches for determining dynamic synchronization resource requirements. Computers and Their Applications 1998: 385-388
19		José G. Delgado-Frias, Richard Diaz: A VLSI Self-Compacting Buffer for DAMQ Communication Switches. Great Lakes Symposium on VLSI 1998: 128-133
18		Adger E. Harvin III, José G. Delgado-Frias: A Dictionary Machine Emulation on a VLSI Computing Tree System. Great Lakes Symposium on VLSI 1998: 134-139
17		José G. Delgado-Frias, Jabulani Nyathi: A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI 1998: 59-64
16		Chien-Ying Lu, José G. Delgado-Frias, Wei Lin: A Clustering and Genetic Scheme for Large Tsp Optimization Problems. Cybernetics and Systems 29(2): 137-157 (1998)
15		Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: Executing tree routing algorithms on a high-performance pattern associative router. Journal of Systems Architecture 44(11): 849-866 (1998)
	1996
14		Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Interconnection Network Adaptive Algorithms. Euro-Par, Vol. I 1996: 213-217
13		José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville: A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251
12		Ming Zhang, Stamatis Vassiliadis, José G. Delgado-Frias: Sigmoid Generators for Neural Computing Using Piecewise Approximations. IEEE Trans. Computers 45(9): 1045-1049 (1996)
11		Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A Flexible Bit-Pattern Associative Router for Interconnection Networks. IEEE Trans. Parallel Distrib. Syst. 7(5): 477-485 (1996)
	1995
10		Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106
9		Daniel G. Rice, José G. Delgado-Frias, Douglas H. Summerville: A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks. Parallel and Distributed Computing and Systems 1995: 238-242
8		Adger E. Harvin III, José G. Delgado-Frias: A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing. Parallel and Distributed Computing and Systems 1995: 455-458
7		Joonho Park, Stamatis Vassiliadis, José G. Delgado-Frias: Flexible oblivious router architecture. IBM Journal of Research and Development 39(3): 315-330 (1995)
6		Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias: The multi-associative branch target buffer: a cost effective BTB mechanism. Microprocessing and Microprogramming 41(3): 211-225 (1995)
	1994
5		Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis: A High Performance Pattern Associative Oblivious Router for Tree Topologies. IPPS 1994: 541-545
4		Joonho Park, Brian W. O'Krafka, Stamatis Vassiliadis, José G. Delgado-Frias: Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers. SC 1994: 713-722
3		Chuan-Jen Chang, Stamatis Vassiliadis, José G. Delgado-Frias: An investigation of binary CLA and ripple CMOS adder designs. Microprocessing and Microprogramming 40(1): 1-21 (1994)
	1991
2		Robert H. Payne, José G. Delgado-Frias: MPU: A N-Tuple Matching Processor. ICCD 1991: 225-228
	1988
1		José G. Delgado-Frias, D. M. Green: BVE: a wafer-scale engine for differential equation computation. ICS 1988: 101-107

Coauthor Index

1	Valentine C. Aikens II	[10] [21]
2	Fredrick L. Anderson	[31]
3	Fred L. Anderson IV	[26]
4	Hamid R. Arabnia	[38]
5	Steven M. Barber	[10]
6	Laxmi N. Bhuyan	[22]
7	Daniel R. Blum	[25] [35] [45]
8	Chuan-Jen Chang	[3]
9	Weili Chu	[6]
10	Richard Diaz	[19]
11	Jason Van Dyken	[53]
12	Joseph Giordano	[23]
13	Vladimir I. Gorodetski	[23]
14	D. M. Green	[1]
15	R. Guo	[49]
16	Ruirui Guo	[54]
17	Adger E. Harvin III	[8] [18]
18	Rongsen He	[42] [44] [47]
19	Yiming Li	[38] [43]
20	H. Lin	[48]
21	Wei Lin	[16]
22	Jin Liu	[34]
23	Chien-Ying Lu	[16]
24	H. Lui	[50]
25	Dennis L. McGee	[23]
26	Sirisha Medidi	[48] [50] [53]
27	Chester L. Miller	[13]
28	Mitchell J. Myjak	[27] [28] [31] [35] [37] [40] [51]
29	Mohammed Y. Niamat	[43]
30	Jabulani Nyathi	[13] [17] [22] [29] [33]
31	Brian W. O'Krafka	[4]
32	Joonho Park	[4] [7]
33	Robert H. Payne	[2]
34	Gerald G. Pechanek	[10] [21]
35	Leonard J. Popyack	[23]
36	Girish B. Ratanpal	[24]
37	Daniel G. Rice	[9] [14]
38	Kylan Robinson	[55]
39	Ray Robert Rydberg III	[29] [33]
40	Salam N. Salloum	[38]
41	Victor A. Skormin	[23]
42	Dimitrios Soudris (D. J. Soudris)	[43]
43	Douglas H. Summerville	[5] [9] [11] [13] [14] [15] [20]
44	Alexander O. Tarakanov	[23]
45	Suryanarayana Tatapudi	[32] [36] [41]
46	Michael A. Turi	[52]
47	Stamatis Vassiliadis	[3] [4] [5] [6] [7] [10] [11] [12] [15] [21]
48	Srinivasa Vemuru	[43]
49	Andy Widjaja	[30]
50	Laurence Tianruo Yang	[38] [43]
51	Ming Zhang	[12]
52	Li Zhao	[39] [46]

Colors in the list of coauthors