Rajagopalan Desikan

	2006
6		Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler: Design and Implementation of the TRIPS Primary Memory System. ICCD 2006
5		Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger: Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. MICRO 2006: 480-491
	2004
4		Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler: Scalable selective re-execution for EDGE architectures. ASPLOS 2004: 120-132
3		Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler: Scalable Hardware Memory Disambiguation for High-ILP Processors. IEEE Micro 24(6): 118-127 (2004)
	2003
2		Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler: Scalable Hardware Memory Disambiguation for High ILP Processors. MICRO 2003: 399-410
	2002
1		Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, Llorenc Cruz, Fernando Latorre, Antonio González, Mateo Valero: Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Computer Architecture News 30(1): 2-4 (2002)

Coauthor Index

1	Doug Burger	[1] [2] [3] [4] [5] [6]
2	Llorenc Cruz	[1]
3	Saurabh Drolia	[5]
4	Antonio González	[1]
5	Madhu Saravana Sibi Govindan (M. S. Govindan)	[5]
6	Paul Gratz	[5]
7	Divya Gulati	[5]
8	Heather Hanson	[5]
9	Stephen W. Keckler	[1] [2] [3] [4] [5] [6]
10	Changkyu Kim	[5]
11	Fernando Latorre	[1]
12	Haiming Liu	[5]
13	Robert G. McDonald	[5] [6]
14	Charles R. Moore	[2] [3]
15	Ramadass Nagarajan	[5]
16	Nitya Ranganathan	[5]
17	Karthikeyan Sankaralingam	[5]
18	Simha Sethumadhavan	[2] [3] [4] [5] [6]
19	Sadia Sharif	[5]
20	Premkishore Shivakumar	[5]
21	Mateo Valero	[1]