| 2009 | ||
|---|---|---|
| 60 | Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen: Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI 2009: 51-56 | |
| 59 | Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong: Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 | |
| 2008 | ||
| 58 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI 2008: 89-94 | |
| 57 | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 | |
| 56 | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto: Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 | |
| 55 | Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto: Cache miss reduction through hardware-assisted loop optimization. CSCWD 2008: 129-134 | |
| 54 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng: A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23 | |
| 53 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED 2008: 321-324 | |
| 52 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Transactions 91-A(6): 1478-1487 (2008) | |
| 51 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Transactions 91-A(9): 2456-2464 (2008) | |
| 2007 | ||
| 50 | Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 | |
| 49 | Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong: Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 | |
| 48 | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 | |
| 47 | Kang Zhao, Jinian Bian, Sheqin Dong: A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD 2007: 121-126 | |
| 46 | Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 | |
| 45 | Hongjie Bai, Sheqin Dong, Xianlong Hong: Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840 | |
| 44 | Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong: Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 | |
| 43 | Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma: An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 | |
| 42 | Yaoguang Wei, Sheqin Dong, Xianlong Hong: APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integration 40(4): 406-419 (2007) | |
| 2006 | ||
| 41 | Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma: A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 | |
| 40 | Di Long, Xianlong Hong, Sheqin Dong: Signal-path driven partition and placement for analog circuit. ASP-DAC 2006: 694-699 | |
| 39 | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen: Buffer planning based on block exchanging. ISCAS 2006 | |
| 38 | Sheqin Dong, Shuyi Zheng, Xianlong Hong: Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS 2006 | |
| 37 | Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu: On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS 2006 | |
| 36 | Kang Zhao, Jinian Bian, Sheqin Dong: A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS 2006 | |
| 35 | Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong: A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS 2006 | |
| 34 | Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong: Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS 2006 | |
| 33 | Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong: Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS 2006 | |
| 32 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) | |
| 2005 | ||
| 31 | Rong Liu, Sheqin Dong, Xianlong Hong: Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI 2005: 156-159 | |
| 30 | Renshen Wang, Sheqin Dong, Xianlong Hong: An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118 | |
| 29 | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu: LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC 2005: 1123-1126 | |
| 28 | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen: A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299 | |
| 27 | Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani: A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213 | |
| 26 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 | |
| 25 | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani: Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886 | |
| 24 | Di Long, Xianlong Hong, Sheqin Dong: Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) 2005: 2999-3002 | |
| 23 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 | |
| 22 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng: Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 | |
| 21 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng: Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 | |
| 20 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu: Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 609-621 (2005) | |
| 2004 | ||
| 19 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 | |
| 18 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 | |
| 17 | Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu: Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) 2004: 61-64 | |
| 16 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) | |
| 15 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu: Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) | |
| 2003 | ||
| 14 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 | |
| 13 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu: Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 | |
| 12 | Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu: Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) 2003: 716-719 | |
| 11 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu: Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 | |
| 10 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu: An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 | |
| 9 | Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu: Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18(6): 739-746 (2003) | |
| 2002 | ||
| 8 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. VLSI Design 2002: 387-392 | |
| 7 | Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai: An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) | |
| 2001 | ||
| 6 | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 | |
| 5 | Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu: VLSI block placement using less flexibility first principles. ASP-DAC 2001: 601-604 | |
| 4 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 | |
| 3 | Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: ECBL: an extended corner block list with solution space including optimum placement. ISPD 2001: 150-155 | |
| 2 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu: Floorplanning with abutment constraints based on corner block list. Integration 31(1): 65-77 (2001) | |
| 2000 | ||
| 1 | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu: Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12 | |