Stéphane Donnay

	2007
29		Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941
28		Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance CoRR abs/0710.4723: (2007)
	2006
27		Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. VLSI Syst. 14(1): 23-33 (2006)
26		Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006)
	2005
25		Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275
24		Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005)
23		J. Tubbax, B. Come, Liesbet Van der Perre, Stéphane Donnay, Marc Engels, Hugo De Man, Marc Moonen: Compensation of IQ imbalance and phase noise in OFDM systems. IEEE Transactions on Wireless Communications 4(3): 872-877 (2005)
	2004
22		Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859
21		Gerd Vandersteen, Rik Pintelon, Dimitri Linten, Stéphane Donnay: Extended Subspace Identification of Improper Linear Systems. DATE 2004: 454-459
20		Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93
	2003
19		Jan Craninckx, Stéphane Donnay: 4G terminals: how are we going to design them? DAC 2003: 79-84
18		Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay: Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. DATE 2003: 10624-10629
17		Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. DATE 2003: 10642-10649
16		Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man: An analytic Volterra-series-based model for a MEMS variable capacitor. IEEE Trans. on CAD of Integrated Circuits and Systems 22(2): 124-131 (2003)
15		Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay: Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1215-1227 (2003)
	2002
14		Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404
13		Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay: Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . DATE 2002: 352-356
12		Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst: High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. DATE 2002: 586-591
	2001
11		Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens: Efficient bit-error-rate estimation of multicarrier transceivers. DATE 2001: 164-168
10		Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330
9		Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt: A Mixed-Signal Design Roadmap. IEEE Design & Test of Computers 18(6): 34-46 (2001)
	2000
8		Gerd Vandersteen, Piet Wambacq, Yves Rolain, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens: A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers. DAC 2000: 440-445
7		Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation including power supply noise coupling. DAC 2000: 446-451
6		Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens: Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. DATE 2000: 350-
	1999
5		Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens: A Single-Package Solution for Wireless Transceivers. DATE 1999: 425-
	1998
4		Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen: Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. DATE 1998: 716-720
	1997
3		Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven: High-level synthesis of analog sensor interface front-ends. ED&TC 1997: 56-60
	1995
2		Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen: A high-level design and optimization tool for analog RF receiver front-ends. ICCAD 1995: 550-553
	1994
1		Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts: A Methodology for Analog Design Automation in Mixed-Signal ASICs. EDAC-ETC-EUROASIC 1994: 530-534

Coauthor Index

1	Mustafa Badaroglu	[7] [10] [14] [20] [22] [24] [26] [27] [29]
2	W. van Bokhoven	[3]
3	Ivo Bolsens	[5] [6] [7] [8] [10] [11]
4	Ralf Brederlow	[9]
5	B. Come	[23]
6	Jan Craninckx	[19]
7	Jan Crols	[2]
8	Petr Dobrovolný	[6] [8] [15] [18] [22]
9	Wolfgang Eberle	[17]
10	Marc Engels	[5] [6] [7] [8] [10] [11] [23]
11	Georges G. E. Gielen	[1] [2] [3] [4] [10] [14] [17] [20] [22] [24] [26] [27] [29]
12	Michaël Goffioul	[13]
13	Vincent Gravot	[10]
14	Marc van Heijningen	[7] [10]
15	Manuel Innocent	[16]
16	Wim Kruiskamp	[1] [3]
17	Domine Leenaerts	[1] [3]
18	Francky Leyn	[4]
19	Dimitri Linten	[21]
20	Hugo De Man	[5] [10] [14] [16] [17] [20] [22] [23] [24] [26] [27] [29]
21	Marc Moonen	[23]
22	Liesbet Van der Perre	[23]
23	Rik Pintelon	[21]
24	Geert Van der Plas	[20] [22] [24] [25] [26] [27] [28] [29]
25	Yves Rolain	[8] [11]
26	Willy M. C. Sansen	[1] [3] [4] [16]
27	Joseph Sauerer	[9]
28	Johan Schoukens	[11]
29	Charlotte Soens	[25] [28]
30	Michiel Steyaert	[2]
31	Koen Swings	[1]
32	Harrie A. C. Tilmans	[16]
33	Kris Tiri	[14] [26]
34	J. Tubbax	[23]
35	Jan Vandenbussche	[4]
36	Gerd Vandersteen	[8] [11] [12] [13] [15] [17] [18] [21] [22]
37	Ingrid Verbauwhede	[14] [26]
38	Frans Verbeyst	[12]
39	Maarten Vertregt	[9]
40	Piet Wambacq	[5] [6] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [20] [22] [24] [25] [26] [27] [28] [29]
41	Werner Weber	[9]
42	Hocine Ziad	[5]