Daniel M. Dreps Coauthor index DBLP Vis pubzone.org

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DBLP keys2009
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED 2009: 451-458
2008
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLing Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng: Low power passive equalizer optimization using tritonic step response. DAC 2008: 570-573
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLing Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56
2007
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth: High-speed interconnect and packaging design of the IBM System z9 processor cage. IBM Journal of Research and Development 51(1/2): 37-52 (2007)

Coauthor Index

1James F. Buckwalter [2] [4]
2Chung-Kuan Cheng [2] [3] [4]
3Kenneth L. Christian [1]
4Alina Deutsch [2] [3] [4]
5Gary F. Goth [1]
6Hubert Harrer [1]
7Andreas Huber [1]
8George A. Katopis [2] [3] [4]
9Ernest S. Kuh [2] [3] [4]
10Wolfgang Scholz [1]
11Bao G. Truong [1]
12Renshen Wang [2]
13Thomas-Michael Winkel [1]
14Wenjian Yu [2] [3]
15Ling Zhang [2] [3] [4]
16Yulei Zhang [2] [4]
17Tingdong Zhou [1]
18Haikun Zhu [3]

Copyright © Fri Nov 27 15:43:12 2009 by Michael Ley (ley@uni-trier.de)