Prashant Dubey

	2008
5		Akhil Garg, Prashant Dubey: On Chip Jitter Measurement through a High Accuracy TDC. ISQED 2008: 844-847
	2007
4		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Built in Defect Prognosis for Embedded Memories. DDECS 2007: 167-172
3		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: GALS Based Shared Test Architecture for Embedded Memories. ISCAS 2007: 157-160
2		Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI 2007: 171-178
	2006
1		Akhil Garg, Prashant Dubey: Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT 2006: 166-174

Coauthor Index

1	Sravan Kumar Bhaskarani	[2] [3] [4]
2	Akhil Garg	[1] [2] [3] [4] [5]