| 2008 |
|---|
| 102 | | Per Stenström,
Michel Dubois,
Manolis Katevenis,
Rajiv Gupta,
Theo Ungerer:
High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings
Springer 2008 |
| 101 | EE | Federico Tajariol,
Jean-Michel Adam,
Michel Dubois:
Seeing the Face and Observing the Actions: The Effects of Nonverbal Cues on Mediated Tutoring Dialogue.
Intelligent Tutoring Systems 2008: 480-489 |
| 2007 |
|---|
| 100 | | Utpal Banerjee,
José Moreira,
Michel Dubois,
Per Stenström:
Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007
ACM 2007 |
| 99 | EE | Md. Mafijul Islam,
Alexander Busck,
Mikael Engbom,
Simji Lee,
Michel Dubois,
Per Stenström:
Loop-level Speculative Parallelism in Embedded Applications.
ICPP 2007: 3 |
| 98 | EE | Michel Dubois,
Hyunyoung Lee,
Lan Lin:
STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems.
IPDPS 2007: 1-8 |
| 97 | EE | Marc-Eric Bobillier-Chaumon,
Michel Dubois,
Françoise Sandoz-Guermond:
Study of conditions of use of E-services accessible to visually disabled persons
CoRR abs/0712.2168: (2007) |
| 96 | EE | Jianwei Chen,
Michel Dubois,
Per Stenström:
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators.
IEEE Micro 27(4): 34-48 (2007) |
| 2006 |
|---|
| 95 | | Laxmi N. Bhuyan,
Michel Dubois,
Will Eatherton:
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2006, San Jose, California, USA, December 3-5, 2006
ACM 2006 |
| 94 | EE | Jaeheon Jeong,
Per Stenström,
Michel Dubois:
Simple penalty-sensitive replacement policies for caches.
Conf. Computing Frontiers 2006: 341-352 |
| 93 | EE | Jaeheon Jeong,
Michel Dubois:
Cache Replacement Algorithms with Nonuniform Miss Costs.
IEEE Trans. Computers 55(4): 353-365 (2006) |
| 2005 |
|---|
| 92 | EE | Nasir Mohyuddin,
Rashed Bhatti,
Michel Dubois:
Controlling leakage power with the replacement policy in slumberous caches.
Conf. Computing Frontiers 2005: 161-170 |
| 91 | EE | Xiaogang Qiu,
Michel Dubois:
Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 16(7): 612-623 (2005) |
| 2004 |
|---|
| 90 | EE | Michel Dubois:
Fighting the memory wall with assisted execution.
Conf. Computing Frontiers 2004: 168-180 |
| 89 | EE | Martin Kämpe,
Per Stenström,
Michel Dubois:
Self-correcting LRU replacement policies.
Conf. Computing Frontiers 2004: 181-191 |
| 88 | EE | Xiaogang Qiu,
Michel Dubois:
Tolerating Late Memory Traps in Dynamically Scheduled Processors.
IEEE Trans. Computers 53(6): 732-743 (2004) |
| 2003 |
|---|
| 87 | EE | Jaeheon Jeong,
Michel Dubois:
Cost-Sensitive Cache Replacement Algorithms.
HPCA 2003: 327- |
| 86 | EE | Jianwei Chen,
Michel Dubois,
Per Stenström:
Integrating complete-system and user-level performance/power simulators: the SimWattch approach.
ISPASS 2003: 1-10 |
| 85 | | Adrian Moga,
Michel Dubois:
Scalability implications of software-implemented coherence.
Comput. Syst. Sci. Eng. 18(1): 7-15 (2003) |
| 2002 |
|---|
| 84 | EE | Martin Kämpe,
Per Stenström,
Michel Dubois:
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.
HPCA 2002: 223-232 |
| 83 | | Michel Dubois,
Jaeheon Jeong,
Ashwini K. Nanda:
Shared cache architectures for decision support systems.
Perform. Eval. 49(1/4): 283-298 (2002) |
| 2001 |
|---|
| 82 | EE | Xiaogang Qiu,
Michel Dubois:
Towards Virtually-Addressed Memory Hierarchies.
HPCA 2001: 51-62 |
| 2000 |
|---|
| 81 | EE | Fong Pong,
Michel Dubois:
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models.
IEEE Trans. Parallel Distrib. Syst. 11(9): 989-1006 (2000) |
| 80 | EE | Michel Dubois,
Isolde Vial:
Multimedia design: the effects of relating multimodal information.
J. Comp. Assisted Learning 16(2): 157-165 (2000) |
| 79 | | Jonas Skeppstedt,
Michel Dubois:
Compiler Controlled Prefetching for Multiprocessors Using Low-Overhead Traps and Prefetch Engines.
J. Parallel Distrib. Comput. 60(5): 585-615 (2000) |
| 1999 |
|---|
| 78 | EE | Xiaogang Qiu,
Michel Dubois:
Tolerating Late Memory Traps in ILP Processors.
ISCA 1999: 76-87 |
| 77 | EE | Jaeheon Jeong,
Michel Dubois:
Optimal Replacements in Caches with Two Miss Costs.
SPAA 1999: 155-164 |
| 1998 |
|---|
| 76 | EE | Michel Dubois,
Christoph Scheurich,
Faye A. Briggs:
Memory Access Buffering in Multiprocessors.
25 Years ISCA: Retrospectives and Reprints 1998: 320-328 |
| 75 | EE | Michel Dubois,
Christoph Scheurich:
Retrospective: Memory Access Buffering in Multiprocessors.
25 Years ISCA: Retrospectives and Reprints 1998: 48-50 |
| 74 | EE | Adrian Moga,
Michel Dubois:
The Effectiveness of SRAM Network Caches in Clustered DSMs.
HPCA 1998: 103-112 |
| 73 | EE | Xiaogang Qiu,
Michel Dubois:
Options for Dynamic Address Translation in COMAs.
ISCA 1998: 214-225 |
| 72 | EE | Christopher Ho,
Heidi E. Ziegler,
Michel Dubois:
In-Memory Directories: Eliminating the Cost of Directories in CC-NUMAs.
SPAA 1998: 222-230 |
| 71 | EE | Michel Dubois,
Jaeheon Jeong,
Yong Ho Song,
Adrian Moga:
Rapid Hardware Prototyping on RPM-2.
IEEE Design & Test of Computers 15(3): 112-118 (1998) |
| 70 | | Fong Pong,
Michael C. Browne,
Gunes Aybay,
Andreas Nowatzyk,
Michel Dubois:
Design Verification of the S3.mp Cache-Coherent Shared-Memory System.
IEEE Trans. Computers 47(1): 135-140 (1998) |
| 69 | | Fredrik Dahlgren,
Michel Dubois,
Per Stenström:
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors.
IEEE Trans. Computers 47(10): 1041-1055 (1998) |
| 68 | EE | Fong Pong,
Michel Dubois:
Formal Verification of Complex Coherence Protocols Using Symbolic State Models.
J. ACM 45(4): 557-587 (1998) |
| 67 | | Kangwoo Lee,
Michel Dubois:
Empirical Models of Miss Rates.
Parallel Computing 24(2): 205-219 (1998) |
| 1997 |
|---|
| 66 | EE | Kangwoo Lee,
Woo-Jong Han,
Michel Dubois:
Bottleneck-Free Interconnect and IO Subsystem in SPAX.
ICPADS 1997: 524-533 |
| 65 | EE | Adrian Moga,
Michel Dubois,
Alain Gefflaut:
Hardware Versus Software Implementation of COMA.
ICPP 1997: 248-256 |
| 64 | EE | Jonas Skeppstedt,
Michel Dubois:
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps.
ICPP 1997: 298-305 |
| 63 | | Per Stenström,
Mats Brorsson,
Fredrik Dahlgren,
Håkan Grahn,
Michel Dubois:
Boosting the Performance of Shared Memory Multiprocessors.
IEEE Computer 30(7): 63-70 (1997) |
| 1996 |
|---|
| 62 | EE | Fong Pong,
Michel Dubois:
Formal Verification of Delayed Consistency Protocols.
IPPS 1996: 124-131 |
| 61 | EE | Adrian Moga,
Michel Dubois:
Performance of Asynchronous Linear Iterations with Random Delays.
IPPS 1996: 625-629 |
| 60 | EE | Fong Pong,
Michel Dubois:
Verification Techniques for Cache Coherence Protocols.
ACM Comput. Surv. 29(1): 82-126 (1996) |
| 59 | | Aydin Üresin,
Michel Dubois:
Effects of Asynchronism on the Convergence Rate of Iterative Algorithms.
J. Parallel Distrib. Comput. 34(1): 66-81 (1996) |
| 1995 |
|---|
| 58 | | Fong Pong,
Andreas Nowatzyk,
Gunes Aybay,
Michel Dubois:
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study.
Euro-Par 1995: 287-300 |
| 57 | EE | Koray Öner,
Luiz André Barroso,
Sasan Iman,
Jaeheon Jeong,
Krishnan Ramamurthy,
Michel Dubois:
The Design of RPM: An FPGA-based Multiprocessor Emulator.
FPGA 1995: 60-66 |
| 56 | | Luiz André Barroso,
Sasan Iman,
Jaeheon Jeong,
Koray Öner,
Michel Dubois:
RPM: A Rapid Prototyping Engine for Multiprocessor Systems.
IEEE Computer 28(2): 26-34 (1995) |
| 55 | | Luiz André Barroso,
Michel Dubois:
Performance Evaluation of the Slotted Ring Multiprocessor.
IEEE Trans. Computers 44(7): 878-890 (1995) |
| 54 | EE | Fredrik Dahlgren,
Michel Dubois,
Per Stenström:
Sequential Hardware Prefetching in Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 6(7): 733-746 (1995) |
| 53 | EE | Fong Pong,
Michel Dubois:
A New Approach for the Verification of Cache Coherence Protocols.
IEEE Trans. Parallel Distrib. Syst. 6(8): 773-787 (1995) |
| 52 | | Michel Dubois,
Jonas Skeppstedt,
Per Stenström:
Essential Misses and Data Traffic in Coherence Protocols.
J. Parallel Distrib. Comput. 29(2): 108-125 (1995) |
| 1994 |
|---|
| 51 | | Fong Pong,
Per Stenström,
Michel Dubois:
An Integrated Methodology for the Verification of Directory-Based Cache Protocols.
ICPP (1) 1994: 158-165 |
| 50 | | Fredrik Dahlgren,
Michel Dubois,
Per Stenström:
Combined Performance Gains of Simple Cache Protocol Extensions.
ISCA 1994: 187-197 |
| 1993 |
|---|
| 49 | | Fredrik Dahlgren,
Michel Dubois,
Per Stenström:
Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors.
ICPP 1993: 56-63 |
| 48 | | Yung-Syau Chen,
Michel Dubois:
Cache Protocols with Partial Block Invalidations.
IPPS 1993: 16-23 |
| 47 | | Luiz André Barroso,
Michel Dubois:
The Performance of Cache-Coherent Ring-based Multiprocessors.
ISCA 1993: 268-277 |
| 46 | | Michel Dubois,
Jonas Skeppstedt,
Livio Ricciulli,
Krishnan Ramamurthy,
Per Stenström:
The Detection and Elimination of Useless Misses in Multiprocessors.
ISCA 1993: 88-97 |
| 45 | EE | Koray Öner,
Michel Dubois:
Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures.
International Conference on Supercomputing 1993: 338-347 |
| 44 | | Jacqueline Chame,
Michel Dubois:
Cache Inclusion and Processor Sampling in Multiprocessor Simulations.
SIGMETRICS 1993: 36-47 |
| 43 | EE | Fong Pong,
Michel Dubois:
The Verification of Cache Coherence Protocols.
SPAA 1993: 11-20 |
| 42 | | Fong Pong,
Michel Dubois:
Correctness of a Directory-Based Cache Coherence Protocol: Early Experience.
SPDP 1993: 37-44 |
| 1992 |
|---|
| 41 | | Ashfaq A. Khokhar,
Michel Dubois:
Matching Algorithms and Architecture in Hierarchical Shared-Memory Multiprocessor (HMS) Systems.
IPPS 1992: 558-561 |
| 40 | | Michel Dubois,
Luiz André Barroso,
Yung-Syau Chen,
Koray Öner:
Scalability Problems in Multiprocessors with Private Caches.
PARLE 1992: 211-230 |
| 39 | | Michel Dubois:
Special Issue on Memory System Architectures for Scalable Multiprocessors.
J. Parallel Distrib. Comput. 15(4): 303-304 (1992) |
| 1991 |
|---|
| 38 | | Luiz André Barroso,
Michel Dubois:
Cache Coherence on a Slotted Ring.
ICPP (1) 1991: 230-237 |
| 37 | | Jin-Chin Wang,
Michel Dubois,
Faye A. Briggs:
Analytical Modeling for Finite Cache Effects.
ICPP (1) 1991: 287-291 |
| 36 | EE | Michel Dubois,
Jin-Chin Wang,
Luiz André Barroso,
Kangwoo Lee,
Yung-Syau Chen:
Delayed consistency and its effects on the miss rate of parallel programs.
SC 1991: 197-206 |
| 35 | | Michel Dubois,
Faye A. Briggs:
The Run-Time Efficiency of Parallel Asynchronous Algorithms.
IEEE Trans. Computers 40(11): 1260-1266 (1991) |
| 34 | | Michel Dubois,
Jin-Chin Wang:
Shared Block Contention in a Cache Coherence Protocol.
IEEE Trans. Computers 40(5): 640-644 (1991) |
| 33 | | Christoph Scheurich,
Michel Dubois:
Lockup-free Caches in High-Performance Multiprocessors.
J. Parallel Distrib. Comput. 11(1): 25-36 (1991) |
| 1990 |
|---|
| 32 | | Anastasios A. Economides,
Michel Dubois:
Transient Models of Bus-Based Multiprocessors.
ICPP (1) 1990: 153-160 |
| 31 | | Aydin Üresin,
Michel Dubois:
Asynchronous Iterations with Bounded Delay.
ICPP (3) 1990: 236-243 |
| 30 | | Sharad Mehrotra,
Chien-Ming Cheng,
Kai Hwang,
Michel Dubois,
Dhabaleswar K. Panda:
Algorithm-Driven Simulation and Performance Projection of a RISC-based Orthogonal Multiprocessor.
ICPP (3) 1990: 244-253 |
| 29 | EE | Kai Hwang,
Michel Dubois,
Dhabaleswar K. Panda,
S. Rao,
Shisheng Shang,
Aydin Üresin,
W. Mao,
H. Nair,
M. Lytwyn,
F. Hsieh,
J. Liu,
Sharad Mehrotra,
Chien-Ming Cheng:
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses.
ICS 1990: 7-22 |
| 28 | | Jin-Chin Wang,
Michel Dubois:
Performance comparison of cache coherence protocols based on the access burst model.
Comput. Syst. Sci. Eng. 5(3): 147-158 (1990) |
| 27 | | Shreekant S. Thakkar,
Michel Dubois,
Anthony T. Laundrie,
Gurindar S. Sohi,
David V. James,
Stein Gjessing,
Manu Thapar,
Bruce Delagi,
Michael J. Carlton,
Alvin M. Despain:
Scalable Shared-Memory Multiprocessor Architectures.
IEEE Computer 23(6): 71-83 (1990) |
| 26 | | Michel Dubois,
Shreekant S. Thakkar:
Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue.
IEEE Computer 23(6): 9-11 (1990) |
| 25 | EE | Michel Dubois,
Christoph Scheurich:
Memory Access Dependencies in Shared-Memory Multiprocessors.
IEEE Trans. Software Eng. 16(6): 660-673 (1990) |
| 24 | EE | Aydin Üresin,
Michel Dubois:
Parallel Asynchronous Algorithms for Discrete Data
J. ACM 37(3): 588-606 (1990) |
| 1989 |
|---|
| 23 | | Christoph Scheurich,
Michel Dubois:
Dynamic Page Migration in Multiprocessors with Distributed Global Memory.
IEEE Trans. Computers 38(8): 1154-1163 (1989) |
| 22 | | Aydin Üresin,
Michel Dubois:
Sufficient conditions for the convergence of asynchronous iterations.
Parallel Computing 10(1): 83-92 (1989) |
| 1988 |
|---|
| 21 | | Christoph Scheurich,
Michel Dubois:
Dynamic Page Migration in Multiprocessors with Distributed Global Memory.
ICDCS 1988: 162-169 |
| 20 | | Christoph Scheurich,
Michel Dubois:
Concurrent Miss Resolution in Multiprocessor Caches.
ICPP (1) 1988: 118-125 |
| 19 | | Michel Dubois,
Jin-Chin Wang:
Shared Data Contention in a Cache Coherence Protocol.
ICPP (1) 1988: 146-155 |
| 18 | EE | Christoph Scheurich,
Michel Dubois:
The design of a lockup-free cache for high-performance multiprocessors.
SC 1988: 352-359 |
| 17 | | Michel Dubois,
Christoph Scheurich,
Faye A. Briggs:
Synchronization, Coherence, and Event Ordering in Multiprocessors.
IEEE Computer 21(2): 9-21 (1988) |
| 16 | | Michel Dubois:
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses.
IEEE Trans. Computers 37(1): 58-70 (1988) |
| 1987 |
|---|
| 15 | | Michel Dubois:
Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors.
ICPP 1987: 255-257 |
| 14 | | Aydin Üresin,
Michel Dubois:
Asynchronous Relaxation of Non-Numerical Data.
ICPP 1987: 499-501 |
| 13 | | Christoph Scheurich,
Michel Dubois:
Correct Memory Operation of Cache-Based Multiprocessors.
ISCA 1987: 234-243 |
| 1986 |
|---|
| 12 | | Aydin Üresin,
Michel Dubois:
Generalized Asynchronous Iterations.
CONPAR 1986: 272-278 |
| 11 | | Michel Dubois,
Faye A. Briggs,
Indira Patil,
Meera Balakrishnan:
Trace-Driven Simulations of Parallel and Distributed Algorithms in Multiprocessors.
ICPP 1986: 909-916 |
| 10 | | Michel Dubois,
Christoph Scheurich,
Faye A. Briggs:
Memory Access Buffering in Multiprocessors.
ISCA 1986: 434-442 |
| 1985 |
|---|
| 9 | | Michel Dubois:
A Cache-Based Multiprocessor with High Efficiency.
ICPP 1985: 646-648 |
| 8 | | Michel Dubois:
A Cache-Based Multiprocessor with High Efficiency.
IEEE Trans. Computers 34(10): 968-972 (1985) |
| 1983 |
|---|
| 7 | | Faye A. Briggs,
Michel Dubois:
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories.
IEEE Trans. Computers 32(1): 48-59 (1983) |
| 1982 |
|---|
| 6 | EE | Michel Dubois,
Faye A. Briggs:
Effects of cache coherency in multiprocessors.
ISCA 1982: 299-308 |
| 5 | | Michel Dubois,
Faye A. Briggs:
Effects of Cache Coherency in Multiprocessors.
IEEE Trans. Computers 31(11): 1083-1099 (1982) |
| 4 | | Michel Dubois,
Faye A. Briggs:
Performance of Synchronized Iterative Processes in Multiprocessor Systems.
IEEE Trans. Software Eng. 8(4): 419-431 (1982) |
| 1981 |
|---|
| 3 | | Michel Dubois,
Faye A. Briggs:
Efficient Interprocessor Communications for MIMD Multiprocessor Systems.
ISCA 1981: 187-196 |
| 2 | | Faye A. Briggs,
Michel Dubois,
Kai Hwang:
Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS.
ISCA 1981: 67-80 |
| 1 | | Faye A. Briggs,
Michel Dubois:
Performance of Cache-Based Multiprocessors.
SIGMETRICS 1981: 181-190 |
