Nikil Dutt
List of publications from the DBLP Bibliography Server - FAQ
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 | 2009 | |
|---|---|---|
| 259 |      | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. ASP-DAC 2009: 25-30 |
| 258 | | Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir: TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE 2009: 340-345 |
| 257 | | Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha: Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. ESTImedia 2009: 45-54 |
| 256 | | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. VLSI Design 2009: 499-504 |
| 255 | | Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi: System-level PVT variation-aware power exploration of on-chip communication architectures. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 254 | | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 8(3): (2009) |
| 253 | | Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek: Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 461-465 (2009) |
| 252 | | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek: Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 554-567 (2009) |
| 251 | | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum: A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks 22(5-6): 791-800 (2009) |
| 2008 | ||
| 250 | | Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian: Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. ACM Multimedia 2008: 319-328 |
| 249 | | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. ASP-DAC 2008: 328-333 |
| 248 | | Sudeep Pasricha, Nikil Dutt: ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. ASP-DAC 2008: 789-794 |
| 247 | | Nikil Dutt: Quo vadis, BTSoC (Billion Transistor SoC)? ASP-DAC 2008: 809 |
| 246 | | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: Methodology for multi-granularity embedded processor power model generation for an ESL design flow. CODES+ISSS 2008: 255-260 |
| 245 | | Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini: ESL hand-off: fact or EDA fiction? DAC 2008: 310-312 |
| 244 | | Nikil Dutt: Memory-aware NoC Exploration and Design. DATE 2008: 1128-1129 |
| 243 | | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. DATE 2008: 646-651 |
| 242 | | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian: Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. DIPES 2008: 213-225 |
| 241 | | Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian: Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems. DIPES 2008: 23-34 |
| 240 | | Amin Khajeh Djahromi, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: Cross-layer co-exploration of exploiting error resilience for video over wireless applications. ESTImedia 2008: 13-18 |
| 239 | | Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha: A framework for memory-aware multimedia application mapping on chip-multiprocessors. ESTImedia 2008: 89-94 |
| 238 | | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED 2008: 470-475 |
| 237 | | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko: Compiler driven data layout optimization for regular/irregular array access patterns. LCTES 2008: 41-50 |
| 236 | | Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif: Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. VLSI Design 2008: 14-15 |
| 235 | | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt: Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. VLSI Design 2008: 363-370 |
| 234 | | Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi: PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. VLSI Design 2008: 421-427 |
| 233 | | Nikil Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 232 | | Nikil Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 231 | | Nikil D. Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 230 | | Prabhat Mishra, Nikil Dutt: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 229 | | Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 228 | | Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane: Fast exploration of bus-based communication architectures at the CCATB abstraction. ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 227 | | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Register File Power Reduction Using Bypass Sensitive Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1155-1159 (2008) |
| 226 | | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt: Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1439-1452 (2008) |
| 225 | | Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. IJES 3(3): 119-127 (2008) |
| 224 | | Ilya Issenin, Nikil Dutt: Using FORAY Models to Enable MPSoC Memory Optimizations. International Journal of Parallel Programming 36(1): 93-113 (2008) |
| 2007 | ||
| 223 |  | Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 ACM 2007 |
| 222 | | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC 2007: 274-279 |
| 221 | | Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek: Software controlled memory layout reorganization for irregular array access patterns. CASES 2007: 179-188 |
| 220 | | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera: Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC 2007: 771-776 |
| 219 | | Qiang Zhu, Aviral Shrivastava, Nikil Dutt: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. DATE 2007: 1164-1169 |
| 218 | | Gabor Madl, Nikil Dutt, Sherif Abdelwahed: Performance estimation of distributed real-time embedded systems by discrete event simulations. EMSOFT 2007: 183-192 |
| 217 | | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil D. Dutt, Nalini Venkatasubramanian: A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems. FMOODS 2007: 285-300 |
| 216 | | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters. FORMATS 2007: 257-273 |
| 215 | | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: System level power estimation methodology with H.264 decoder prediction IP case study. ICCD 2007: 601-608 |
| 214 | | Ilya Issenin, Nikil Dutt: Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. IESS 2007: 299-312 |
| 213 | | Nikil Dutt: Modeling of Software-Hardware Complexes. IESS 2007: 423-425 |
| 212 | | Radu Cornea, Alex Nicolau, Nikil Dutt: Annotation Integration and Trade-off Analysis for Multimedia Applications. IPDPS 2007: 1-6 |
| 211 | | Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger: Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. PARCO 2007: 767-776 |
| 210 | | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design 2007: 559-564 |
| 209 | | Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha: Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design 2007: 8 |
| 208 | | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Instruction set synthesis with efficient instruction encoding for configurable processors. ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 207 | | Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt: DRDU: A data reuse analysis technique for efficient scratch-pad memory management. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 206 | | Nikil Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 205 | | Ilya Issenin, Nikil Dutt: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations CoRR abs/0710.4640: (2007) |
| 204 | | Mehrdad Reshadi, Nikil Dutt: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation CoRR abs/0710.4643: (2007) |
| 203 | | Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR abs/0710.4820: (2007) |
| 202 | | Shivajit Mohapatra, Nikil Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices. IEEE Journal on Selected Areas in Communications 25(4): 722-737 (2007) |
| 201 | | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek: Automatic Design Space Exploration of Register Bypasses in Embedded Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2102-2115 (2007) |
| 200 | | Sudeep Pasricha, Nikil D. Dutt: A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 408-420 (2007) |
| 199 | | Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007) |
| 198 | | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1454-1464 (2007) |
| 2006 | ||
| 197 | | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Constraint-driven bus matrix synthesis for MPSoC. ASP-DAC 2006: 30-35 |
| 196 | | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC 2006: 491-496 |
| 195 | | Hyunok Oh, Nikil Dutt, Soonhoi Ha: Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. ASP-DAC 2006: 497-502 |
| 194 | | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian: Mitigating soft error failures for multimedia applications by selective data protection. CASES 2006: 411-420 |
| 193 | | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS 2006: 118-123 |
| 192 | | Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. CODES+ISSS 2006: 16-21 |
| 191 | | Ilya Issenin, Nikil Dutt: Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. CODES+ISSS 2006: 294-299 |
| 190 | | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt: System-level power-performance trade-offs in bus matrix communication architecture synthesis. CODES+ISSS 2006: 300-305 |
| 189 | | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. DAC 2006: 49-52 |
| 188 | | Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek: Automatic generation of operation tables for fast exploration of bypasses in embedded processors. DATE 2006: 1197-1202 |
| 187 | | Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217 |
| 186 | | Radu Cornea, Alexandru Nicolau, Nikil D. Dutt: Software annotations for power optimization on mobile devices. DATE 2006: 684-689 |
| 185 | | Sudeep Pasricha, Nikil D. Dutt: COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. DATE 2006: 700-705 |
| 184 | | Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil Dutt, Qiang Zhu: Formal performance evaluation of AMBA-based system-on-chip designs. EMSOFT 2006: 311-320 |
| 183 | | Radu Cornea, Alex Nicolau, Nikil Dutt: Annotation Based Multimedia Streaming Over Wireless Networks. ESTImedia 2006: 47-52 |
| 182 | | Radu Cornea, Alex Nicolau, Nikil Dutt: Video Stream Annotations for Energy Trade-offs in Multimedia Applications. ISPDC 2006: 17-23 |
| 181 | | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Bypass aware instruction scheduling for register file power reduction. LCTES 2006: 173-181 |
| 180 | | Gabor Madl, Nikil Dutt: Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems. SAMOS 2006: 59-68 |
| 179 | | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656 |
| 178 | | Nikil D. Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 11(1): 1-2 (2006) |
| 177 | | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ACM Trans. Design Autom. Electr. Syst. 11(1): 123-146 (2006) |
| 176 | | Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006) |
| 175 | | Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra: A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006) |
| 174 | | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. VLSI Syst. 14(11): 1189-1202 (2006) |
| 173 | | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: FABSYN: floorplan-aware bus architecture synthesis. IEEE Trans. VLSI Syst. 14(3): 241-253 (2006) |
| 172 | | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta: Energy efficient watermarking on mobile devices using proxy-based partitioning. IEEE Trans. VLSI Syst. 14(6): 625-636 (2006) |
| 171 | | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. VLSI Syst. 14(7): 754-762 (2006) |
| 170 | | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Retargetable pipeline hazard detection for partially bypassed processors. IEEE Trans. VLSI Syst. 14(8): 791-801 (2006) |
| 169 | | Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt: Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2904-2918 (2006) |
| 168 | | Minyoung Kim, Hyunok Oh, Nikil Dutt, Alex Nicolau, Nalini Venkatasubramanian: PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh. Mobile Computing and Communications Review 10(3): 58-69 (2006) |
| 2005 | ||
| 167 | | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: A first look at the interplay of code reordering and configurable caches. ACM Great Lakes Symposium on VLSI 2005: 416-421 |
| 166 | | Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane: Automated throughput-driven synthesis of bus-based communication architectures. ASP-DAC 2005: 495-498 |
| 165 | | Jaewon Seo, Nikil D. Dutt: A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. ASP-DAC 2005: 836-841 |
| 164 | | Hyunok Oh, Nikil D. Dutt, Soonhoi Ha: Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs. CASES 2005: 157-165 |
| 163 | | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: Compilation techniques for energy reduction in horizontally partitioned cache architectures. CASES 2005: 90-96 |
| 162 | | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Aggregating processor free time for energy reduction. CODES+ISSS 2005: 154-159 |
| 161 | | Hyunok Oh, Nikil D. Dutt, Soonhoi Ha: Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. CODES+ISSS 2005: 51-56 |
| 160 | | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC 2005: 335-340 |
| 159 | | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: Floorplan-aware automated synthesis of bus-based communication architectures. DAC 2005: 565-570 |
| 158 | | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251 |
| 157 | | Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. DATE 2005: 1264-1269 |
| 156 | | Prabhat Mishra, Nikil D. Dutt: Functional Coverage Driven Test Generation for Validation of Pipelined Processors. DATE 2005: 678-683 |
| 155 | | Mehrdad Reshadi, Nikil D. Dutt: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. DATE 2005: 786-791 |
| 154 | | Ilya Issenin, Nikil D. Dutt: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. DATE 2005: 808-813 |
| 153 | | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices. ESTImedia 2005: 33-38 |
| 152 | | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM 2005: 273-274 |
| 151 | | Jaewon Seo, Taewhan Kim, Nikil D. Dutt: Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD 2005: 450-455 |
| 150 | | Minyoung Kim, Hyunok Oh, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: Probability Based Power Aware Error Resilient Coding. ICDCS Workshops 2005: 307-313 |
| 149 | | Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian: An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices. ICME 2005: 1424-1427 |
| 148 | | Liang Cheng, Stefano Bossi, Shivajit Mohapatra, Magda El Zarki, Nalini Venkatasubramanian, Nikil D. Dutt: Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices. ICN (1) 2005: 662-671 |
| 147 | | Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau, Sandeep K. Shukla, Nalini Venkatasubramanian: A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems. IPDPS 2005 |
| 146 | | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast configurable-cache tuning with a unified second-level cache. ISLPED 2005: 323-326 |
| 145 | | Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt: An Introduction to the Plasma Language. MTV 2005: 12-22 |
| 144 | | Nikil D. Dutt: Editorial. ACM Trans. Design Autom. Electr. Syst. 10(1): 1-2 (2005) |
| 143 | | Partha Biswas, Nikil D. Dutt: Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. IEEE Trans. Computers 54(10): 1216-1226 (2005) |
| 142 | | Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005) |
| 2004 | ||
| 141 | | Sudarshan Banerjee, Nikil D. Dutt: FIFO power optimization for on-chip networks. ACM Great Lakes Symposium on VLSI 2004: 187-191 |
| 140 | | Aviral Shrivastava, Nikil D. Dutt: Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). ASP-DAC 2004: 475-477 |
| 139 | | Sudarshan Banerjee, Nikil D. Dutt: Efficient search space exploration for HW-SW partitioning. CODES+ISSS 2004: 122-127 |
| 138 | | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: Analytical models for leakage power estimation of memory array structures. CODES+ISSS 2004: 146-151 |
| 137 | | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Operation tables for scheduling in the presence of incomplete bypassing. CODES+ISSS 2004: 194-199 |
| 136 | | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Fast exploration of bus-based on-chip communication architectures. CODES+ISSS 2004: 242-247 |
| 135 | | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Extending the transaction level modeling approach for fast communication architecture exploration. DAC 2004: 113-118 |
| 134 | | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. DAC 2004: 556-561 |
| 133 | | Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt: Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734 |
| 132 | | Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau: Energy-Aware System Design for Wireless Multimedia. DATE 2004: 1124-1131 |
| 131 | | Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. DATE 2004: 114-121 |
| 130 | | Prabhat Mishra, Nikil Dutt: Graph-Based Functional Test Program Generation for Pipelined Processors. DATE 2004: 182-187 |
| 129 | | Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. DATE 2004: 202-207 |
| 128 | | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: Automatic Tuning of Two-Level Caches to Embedded Applications. DATE 2004: 208-213 |
| 127 | | Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta: Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. DATE 2004: 474-479 |
| 126 | | Prabhat Mishra, Nikil D. Dutt: Functional Validation of Programmable Architectures. DSD 2004: 12-19 |
| 125 | | Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta: Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. FPL 2004: 891-899 |
| 124 | | Prabhat Mishra, Nikil D. Dutt, Yaron Kashai: Functional Verification of Pipelined Processors: A Case Study. MTV 2004: 79-84 |
| 123 | | Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Synthesis-driven Exploration of Pipelined Embedded Processors. VLSI Design 2004: 921-926 |
| 122 | | Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau: Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 9(4): 441-470 (2004) |
| 121 | | Prabhat Mishra, Nikil Dutt: Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1): 114-139 (2004) |
| 120 | | Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt: Processor-memory coexploration using an architecture description language. ACM Trans. Embedded Comput. Syst. 3(1): 140-162 (2004) |
| 119 | | Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004) |
| 118 | | Sudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian: Dynamic Backlight Adaptation for Low-Power Handheld Devices. IEEE Design & Test of Computers 21(5): 398-405 (2004) |
| 117 | | Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Using global code motions to improve the quality of results for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 302-312 (2004) |
| 116 | | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1361-1369 (2004) |
| 2003 | ||
| 115 | | Shivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: Integrated power management for video streaming to mobile handheld devices. ACM Multimedia 2003: 582-591 |
| 114 | | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ASAP 2003: 172-182 |
| 113 | | Partha Biswas, Nikil D. Dutt: Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. CASES 2003: 104-112 |
| 112 | | Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt: An efficient retargetable framework for instruction-set simulation. CODES+ISSS 2003: 13-18 |
| 111 | | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. DAC 2003: 758-763 |
| 110 | | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. DATE 2003: 10270-10275 |
| 109 | | Mahesh Mamidipaka, Nikil D. Dutt: On-chip Stack Based Memory Organization for Low Power Embedded Architectures. DATE 2003: 11082-11089 |
| 108 | | Sudeep Pasricha, Shivajit Mohapatra, Manev Luthra, Nikil D. Dutt, Nalini Venkatasubramanian: Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices. ESTImedia 2003: 11-17 |
| 107 | | Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt: Data Organization Exploration for Low-Energy Address Buses. ESTImedia 2003: 128-133 |
| 106 | | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD 2003: 113-119 |
| 105 | | Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Interface Synthesis using Memory Mapping for an FPGA Platform. ICCD 2003: 140-145 |
| 104 | | Mehrdad Reshadi, Nikil D. Dutt: Reducing Compilation Time Overhead in Compiled Simulators. ICCD 2003: 151- |
| 103 | | Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. IEEE International Workshop on Rapid System Prototyping 2003: 226-232 |
| 102 | | Radu Cornea, Nikil D. Dutt, Rajesh K. Gupta, Ingolf Krüger, Alexandru Nicolau, Douglas C. Schmidt, Sandeep K. Shukla: FORGE: A Framework for Optimization of Distributed Embedded Systems Software. IPDPS 2003: 208 |
| 101 | | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Energy-efficient instruction set synthesis for application-specific processors. ISLPED 2003: 330-333 |
| 100 | | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: An algorithm for mapping loops onto coarse-grained reconfigurable architectures. LCTES 2003: 183-188 |
| 99 | | Prabhat Mishra, Nikil D. Dutt: A Methodology for Validation of Microprocessors using Equivalence Checking. MTV 2003: 83-88 |
| 98 | | Marcio Buss, Tony Givargis, Nikil D. Dutt: Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores. RTSS 2003: 275- |
| 97 | | Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri: A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. VLSI Design 2003: 320- |
| 96 | | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. VLSI Design 2003: 461-466 |
| 95 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Access pattern-based memory and connectivity architecture exploration. ACM Trans. Embedded Comput. Syst. 2(1): 33-73 (2003) |
| 94 | | Nikil D. Dutt, Kiyoung Choi: Configurable Processors for Embedded Computing. IEEE Computer 36(1): 120-123 (2003) |
| 93 | | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Design & Test of Computers 20(1): 26-33 (2003) |
| 92 | | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions. IEEE Trans. VLSI Syst. 11(4): 731-737 (2003) |
| 91 | | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt: Adaptive low-power address encoding techniques using self-organizing lists. IEEE Trans. VLSI Syst. 11(5): 827-834 (2003) |
| 2002 | ||
| 90 | | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem: Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903 |
| 89 | | Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE 2002: 168-175 |
| 88 | | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43 |
| 87 | | Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. DATE 2002: 402-408 |
| 86 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory System Connectivity Exploration. DATE 2002: 894-901 |
| 85 | | Prabhat Mishra, Nikil D. Dutt: Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. DIPES 2002: 81-90 |
| 84 | | Preeti Ranjan Panda, Nikil D. Dutt: Memory Architectures for Embedded Systems-On-Chip. HiPC 2002: 647-662 |
| 83 | | Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ICCAD 2002: 649-654 |
| 82 | | Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi: A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ISSS 2002: 120-125 |
| 81 | | Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka: Efficient Power Reduction Techniques for Time Multiplexed Address Buses. ISSS 2002: 207-212 |
| 80 | | Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta: Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. ISSS 2002: 261-266 |
| 79 | | Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458- |
| 2001 | ||
| 78 | | Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi: New directions in compiler technology for embedded systems (embedded tutorial). ASP-DAC 2001: 409-414 |
| 77 | | Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Speculation Techniques for High Level Synthesis of Control Intensive Designs. DAC 2001: 269-272 |
| 76 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Access pattern based local memory customization for low power embedded systems. DATE 2001: 778-784 |
| 75 | | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil Dutt: Low power address encoding using self-organizing lists. ISLPED 2001: 188-193 |
| 74 | | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Conditional speculation and its effects on performance and area for high-level snthesis. ISSS 2001: 171-176 |
| 73 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: APEX. ISSS 2001: 25-32 |
| 72 | | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau: Functional abstraction driven design space exploration of heterogeneous programmable architectures. ISSS 2001: 256-261 |
| 71 | | Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75 |
| 70 | | Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt: Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. VLSI Design 2001: 97-102 |
| 69 | | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg: Data and memory optimization techniques for embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 149-206 (2001) |
| 68 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef: Data Memory Organization and Optimizations in Application-Specific Systems. IEEE Design & Test of Computers 18(3): 56-68 (2001) |
| 67 | | Francky Catthoor, Koen Danckaert, Sven Wuytack, Nikil D. Dutt: Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors. IEEE Design & Test of Computers 18(3): 70-82 (2001) |
| 66 | | Asheesh Khare, Ashok Halambi, Nicolae Savoiu, Peter Grun, Nikil Dutt, Alex Nicolau: V-SAT: A visual specification and analysis tool for system-on-chip exploration. Journal of Systems Architecture 47(3-4): 263-275 (2001) |
| 2000 | ||
| 65 | | Hiroyuki Tomiyama, Nikil D. Dutt: Program path analysis to bound cache-related preemption delay in preemptive real-time systems. CODES 2000: 67-71 |
| 64 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory aware compilation through accurate timing extraction. DAC 2000: 316-321 |
| 63 | | Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis: How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? DATE 2000: 426- |
| 62 | | Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Architecture Exploration of Parameterizable EPIC SOC Architectures. DATE 2000: 748 |
| 61 | | Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Customizing Software Toolkits for Embedded Systems-On-Chip. DIPES 2000: 87-98 |
| 60 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: MIST: An Algorithm for Memory Miss Traffic Management. ICCAD 2000: 431-437 |
| 59 | | Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt: System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. ICCAD 2000: 569-573 |
| 58 | | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Aggressive Memory-Aware Compilation. Intelligent Memory Systems 2000: 147-151 |
| 57 | | Pradip K. Jha, Nikil D. Dutt: High-level library mapping for memories. ACM Trans. Design Autom. Electr. Syst. 5(3): 566-603 (2000) |
| 56 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electr. Syst. 5(3): 682-704 (2000) |
| 55 | | Allen C.-H. Wu, Nikil D. Dutt: Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. VLSI Syst. 8(5): 469-471 (2000) |
| 1999 | ||
| 54 | | Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau: EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. DATE 1999: 485-490 |
| 53 | | Asheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration. EUROMICRO 1999: 1196-1203 |
| 52 | | Nikil D. Dutt, Eric M. Foster: Design of a set-top box system on a chip (abstract). ICCAD 1999: 608 |
| 51 | | Nikil D. Dutt, Brian Kelley: On the rapid prototyping and design of a wireless communication system on a chip (abstract). ICCAD 1999: 609 |
| 50 | | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. ISSS 1999: 44-50 |
| 49 | | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999) |
| 48 | | Preeti Ranjan Panda, Nikil D. Dutt: Low-power memory mapping through reducing address bus activity. IEEE Trans. VLSI Syst. 7(3): 309-320 (1999) |
| 47 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Local memory exploration and optimization in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 3-13 (1999) |
| 1998 | ||
| 46 | | Peter Grun, Florin Balasa, Nikil D. Dutt: Memory size estimation for multimedia applications. CODES 1998: 145-149 |
| 45 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Data Cache Sizing for Embedded Processor Applications. DATE 1998: 925-926 |
| 44 | | Soren Hein, Vijay Nagasamy, Bernhard Rohfleisch, Christoforos E. Kozyrakis, Nikil D. Dutt, Francky Catthoor: Embedded memories in system design - from technology to systems architecture. ICCAD 1998: 1 |
| 43 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Copy Elimination for Parallelizing Compilers. LCPC 1998: 275-289 |
| 42 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Incorporating DRAM access modes into high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 96-109 (1998) |
| 1997 | ||
| 41 | | Pradip K. Jha, Nikil D. Dutt: Library mapping for memories. ED&TC 1997: 288-292 |
| 40 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997: 7-11 |
| 39 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Exploiting off-chip memory access modes in high-level synthesis. ICCAD 1997: 333-340 |
| 38 | | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: A Data Alignment Technique for Improving Cache Performance. ICCD 1997: 587-592 |
| 37 | | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Improving cache Performance Through Tiling and Data Alignment. IRREGULAR 1997: 167-185 |
| 36 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Architectural Exploration and Optimization of Local Memory in Embedded Systems. ISSS 1997: 90- |
| 35 | | Preeti Ranjan Panda, Nikil D. Dutt: Behavioral Array Mapping into Multiport Memories Targeting Low Power. VLSI Design 1997: 268-273 |
| 34 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory data organization for improved cache performance in embedded processor applications. ACM Trans. Design Autom. Electr. Syst. 2(4): 384-409 (1997) |
| 33 | | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: A unified lower bound estimation technique for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 458-472 (1997) |
| 1996 | ||
| 32 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy: A Method for Register Allocation to Loops in Multiple Register File Architectures. IPPS 1996: 28-33 |
| 31 | | Preeti Ranjan Panda, Nikil D. Dutt: Low-power mapping of behavioral arrays to multiple memories. ISLPED 1996: 289-292 |
| 30 | | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory Organization for Improved Data Cache Performance in Embedded Processors. ISSS 1996: 90-95 |
| 29 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy: Optimal register assignment to loops for embedded code generation. ACM Trans. Design Autom. Electr. Syst. 1(2): 251-279 (1996) |
| 28 | | Pradip K. Jha, Nikil D. Dutt: High-level library mapping for arithmetic components. IEEE Trans. VLSI Syst. 4(2): 157-169 (1996) |
| 27 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Elimination of redundant memory traffic in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1354-1364 (1996) |
| 1995 | ||
| 26 | | Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran: Reclocking for high-level synthesis. ASP-DAC 1995 |
| 25 | | Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu: A comprehensive estimation technique for high-level synthesis. ISSS 1995: 122-127 |
| 24 | | Preeti Ranjan Panda, Nikil D. Dutt: 1995 high level synthesis design repository. ISSS 1995: 170-174 |
| 23 | | David J. Kolson, Alexandru Nicolau, Nikil Dutt, Ken Kennedy: Optimal register assignment to loops for embedded code generation. ISSS 1995: 42-47 |
| 1994 | ||
| 22 | | Steven Novack, Alexandru Nicolau, Nikil D. Dutt: A Unified code generation approach using mutation scheduling. Code Generation for Embedded Processors 1994: 203-218 |
| 21 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Minimization of Memory Traffic in High-Level Synthesis. DAC 1994: 149-154 |
| 20 | | Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura: Design Reuse: Fact or Fiction? (Panel). DAC 1994: 562 |
| 19 | | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: Comprehensive lower bound estimation from behavioral descriptions. ICCAD 1994: 182-187 |
| 18 | | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Integrating program transformations in the memory-based synthesis of image and video algorithms. ICCAD 1994: 27-30 |
| 17 | | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioning of Variables for Multiple-Register-File VLIW Architectures. ICPP (1) 1994: 298-301 |
| 16 | | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring. IFIP PACT 1994: 319-322 |
| 15 | | Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi: An Empirical Study on the Effects of Physical Design in High-Level Synthesis. VLSI Design 1994: 11-16 |
| 14 | | Pradip K. Jha, Nikil D. Dutt: Rapid Technology Projection for High-Level Synthesis. VLSI Design 1994: 155-158 |
| 13 | | David J. Kolson, Nikil D. Dutt, Alexandru Nicolau: Ultra Fine-Grain Template-Driven Synthesis. VLSI Design 1994: 25-28 |
| 1993 | ||
| 12 | | Roger P. Ang, Nikil D. Dutt: A Representation for the Binding of RT-Component Functionality to HDL Behavior. CHDL 1993: 263-280 |
| 11 | | Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu: High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. DAC 1993: 336-342 |
| 10 | | Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau: Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. VLSI Design 1993: 198-201 |
| 9 | | Pradip K. Jha, Nikil D. Dutt: Rapid estimation for parameterized components in high-level synthesis. IEEE Trans. VLSI Syst. 1(3): 296-303 (1993) |
| 1992 | ||
| 8 | | Roger P. Ang, Nikil D. Dutt: Equivalent design representations and transformations for interactive scheduling. ICCAD 1992: 332-335 |
| 7 | | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. MICRO 1992: 292-300 |
| 6 | | Daniel Gajski, Nikil D. Dutt: Benchmarking and the Art of Syntesis Tool Comparison. Synthesis for Control Dominated Circuits 1992: 439-453 |
| 1991 | ||
| 5 | | Nikil D. Dutt, James R. Kipps: Bridging High-Level Synthesis to RTL Technology Libraries. DAC 1991: 526-529 |
| 1990 | ||
| 4 | | Nikil D. Dutt, Tedd Hadley, Daniel Gajski: An Intermediate Representation for Behavioral Synthesis. DAC 1990: 14-19 |
| 3 | | Nikil D. Dutt: LEGEND: A Language for Generic Component Library Description. ICCL 1990: 198-207 |
| 2 | | Nikil D. Dutt, Daniel D. Gajski: Design Synthesis and Silicon Compilation. IEEE Design & Test of Computers 7(6): 8-23 (1990) |
| 1989 | ||
| 1 | | Nikil D. Dutt, Daniel Gajski: Designer Controlled Behavioral Synthesis. DAC 1989: 754-757 |