 | 2008 |
|---|
| 7 |       | Avijit Dutta,
Abhijit Jas:
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.
ISQED 2008: 68-73 |
| 2007 |
|---|
| 6 | | Avijit Dutta,
Nur A. Touba:
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code.
DFT 2007: 3-11 |
| 5 | | Avijit Dutta,
Nur A. Touba:
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.
VTS 2007: 349-354 |
| 2006 |
|---|
| 4 | | Avijit Dutta,
Nur A. Touba:
Synthesis of Efficient Linear Test Pattern Generators.
DFT 2006: 206-214 |
| 3 | | Avijit Dutta,
David Z. Pan:
Partial Functional Manipulation Based Wirelength Minimization.
ICCD 2006 |
| 2 | | Avijit Dutta,
Nur A. Touba:
Iterative OPDD Based Signal Probability Calculation.
VTS 2006: 72-77 |
| 2005 |
|---|
| 1 | | Avijit Dutta,
Terence Rodrigues,
Nur A. Touba:
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier.
ISVLSI 2005: 200-205 |
