 | 2007 |
|---|
| 13 |       | Balaji Raman,
Samarjit Chakraborty,
Wei Tsang Ooi,
Santanu Dutta:
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution.
DAC 2007: 738-743 |
| 12 |  | Santanu Dutta:
Recent Trends in the Design of Video Signal Processing IPS and Multimedia SoCs.
SECRYPT 2007: 13 |
| 2005 |
|---|
| 11 | | Santanu Dutta:
Design of Multimillion-Gate Multimedia SoCs: Where do we stand?
ESTImedia 2005: 4 |
| 2003 |
|---|
| 10 | | Santanu Dutta:
Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems.
SBCCI 2003: 145 |
| 2001 |
|---|
| 9 | | Santanu Dutta,
Rune Jensen,
Alf Rieckmann:
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems.
IEEE Design & Test of Computers 18(5): 21-31 (2001) |
| 2000 |
|---|
| 8 | | Santanu Dutta:
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip.
PATMOS 2000: 225-232 |
| 7 | | Santanu Dutta,
Deepak Singh,
Essam Abu-Ghoush,
Vijay Mehra:
Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications.
VLSI Design 2000: 350-359 |
| 1997 |
|---|
| 6 | | Andrew Wolfe,
Jason Fritts,
Santanu Dutta,
Edil S. Tavares Fernandes:
Datapath Design for a VLIW Video Signal Processor.
HPCA 1997: 24- |
| 1995 |
|---|
| 5 | | Santanu Dutta,
Wayne Wolf,
Andrew Wolfe:
VLSI issues in memory-system design for video signal processors.
ICCD 1995: 498- |
| 1994 |
|---|
| 4 | | Santanu Dutta,
Wayne Wolf:
Asymptotic Limits of Video Signal Processing Architectures.
ICCD 1994: 622-625 |
| 3 | | Santanu Dutta,
Sudip Nag,
Kaushik Roy:
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits.
ISCAS 1994: 61-64 |
| 1993 |
|---|
| 2 | | Kaushik Roy,
Sudip Nag,
Santanu Dutta:
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs.
ICCD 1993: 220-223 |
| 1990 |
|---|
| 1 | | Douglas R. Holberg,
Santanu Dutta,
Lawrence T. Pillage:
DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation.
ICCAD 1990: 546-549 |
