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DBLP keys2009
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay: Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. ISCA 2009: 484-495
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay: Rock: A High-Performance Sparc CMT Processor. IEEE Micro 29(2): 6-16 (2009)
2005
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström: A Cost-Effective Main Memory Organization for Future Servers. IPDPS 2005
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström: A Robust Main-Memory Compression Scheme. ISCA 2005: 74-85
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström: Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. ISPASS 2005: 89-99
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Fredrik Warg, Jim Nilsson: An in-depth look at computer performance growth. SIGARCH Computer Architecture News 33(1): 144-147 (2005)
2004
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström: A case for multi-level main memory. WMPI 2004: 1-8
2003
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström: Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. ICPP 2003: 359-368
2002
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMagnus Ekman, Per Stenström, Fredrik Dahlgren: TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ISLPED 2002: 243-246

Coauthor Index

1Shailender Chaudhry [8] [9]
2Robert Cypher [8] [9]
3Fredrik Dahlgren [1]
4Martin Karlsson [8] [9]
5Anders Landin [8] [9]
6Jim Nilsson [4]
7Per Stenström [1] [2] [3] [5] [6] [7]
8Marc Tremblay [8] [9]
9Fredrik Warg [4]
10Sherman Yip [8] [9]
11Håkan Zeffer [8] [9]

Copyright © Tue Feb 9 14:55:32 2010 by Michael Ley (ley@uni-trier.de)