| 2012 | ||
|---|---|---|
| 58 | Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer: CRUISE: cache replacement and utility-aware scheduling. ASPLOS 2012: 249-260 | |
| 57 | Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer: Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184 | |
| 56 | William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer: The gradient-based cache partitioning algorithm. TACO 8(4): 44 (2012) | |
| 2011 | ||
| 55 | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer: Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28 | |
| 54 | Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer: HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417 | |
| 53 | Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer: SHiP: signature-based hit predictor for high performance caching. MICRO 2011: 430-441 | |
| 52 | Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer: PACMan: prefetch-aware cache management for high performance caching. MICRO 2011: 442-453 | |
| 51 | Joel S. Emer, Tryggve Fossum: DEC Alpha. Encyclopedia of Parallel Computing 2011: 535-545 | |
| 2010 | ||
| 50 | Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer: High performance cache replacement using re-reference interval prediction (RRIP). ISCA 2010: 60-71 | |
| 49 | Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer: Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE 2010: 69-72 | |
| 48 | Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer: Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO 2010: 151-162 | |
| 47 | James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi: The Future of Architectural Simulation. IEEE Micro 30(3): 8-18 (2010) | |
| 2009 | ||
| 46 | André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings Springer 2009 | |
| 45 | Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer: Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281 | |
| 44 | Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi: CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA 2009: 289-300 | |
| 43 | Joel S. Emer: Accelerating architecture research. ISPASS 2009 | |
| 42 | Joel S. Emer, Dean M. Tullsen: Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences. IEEE Micro 29(1): 6-9 (2009) | |
| 41 | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. TRETS 2(3): (2009) | |
| 2008 | ||
| 40 | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 | |
| 39 | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 | |
| 38 | Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 | |
| 37 | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) | |
| 2007 | ||
| 36 | Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler: Late-binding: enabling unordered load-store queues. ISCA 2007: 347-357 | |
| 35 | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 | |
| 34 | Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee: Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal. Computer Architecture Letters 7(1): 21-24 (2007) | |
| 33 | Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag: Single-Threaded vs. Multithreaded: Where Should We Focus? IEEE Micro 27(6): 14-24 (2007) | |
| 2005 | ||
| 32 | Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt: The Soft Error Problem: An Architectural Perspective. HPCA 2005: 243-247 | |
| 31 | Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan: Computing Architectural Vulnerability Factors for Address-Based Structures. ISCA 2005: 532-543 | |
| 2004 | ||
| 30 | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt: Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. ISCA 2004: 264-275 | |
| 29 | Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt: Cache Scrubbing in Microprocessors: Myth or Necessity? PRDC 2004: 37-42 | |
| 28 | Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt: Reducing the Soft-Error Rate of a High-Performance Microprocessor. IEEE Micro 24(6): 30-37 (2004) | |
| 2003 | ||
| 27 | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. MICRO 2003: 29-42 | |
| 26 | Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin: Measuring Architectural Vulnerability Factors. IEEE Micro 23(6): 70-75 (2003) | |
| 2002 | ||
| 25 | Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb: A comparative study of arbitration algorithms for the Alpha 21364 pipelined router. ASPLOS 2002: 223-234 | |
| 24 | Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer: Loose Loops Sink Chips. HPCA 2002: 299-310 | |
| 23 | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec: Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281- | |
| 22 | Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson: Performance Simulation Tools. IEEE Computer 35(2): 38-39 (2002) | |
| 21 | Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan: Asim: A Performance Model Framework. IEEE Computer 35(2): 68-76 (2002) | |
| 2000 | ||
| 20 | Alan D. Berenbaum, Joel S. Emer: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada IEEE Computer Society 2000 | |
| 19 | Harish Patil, Joel S. Emer: Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. HPCA 2000: 251-262 | |
| 1999 | ||
| 18 | Timothy Sherwood, Brad Calder, Joel S. Emer: Reducing cache misses using hardware and software page placement. International Conference on Supercomputing 1999: 155-164 | |
| 17 | Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi: The Use of Multithreading for Exception Handling. MICRO 1999: 219-229 | |
| 1998 | ||
| 16 | Joel S. Emer, Douglas W. Clark: A Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 274-283 | |
| 15 | Joel S. Emer, Douglas W. Clark: Retrospective: Characterization of Processor Performance in the VAX-11/780. 25 Years ISCA: Retrospectives and Reprints 1998: 37-38 | |
| 14 | George Z. Chrysos, Joel S. Emer: Memory Dependence Prediction Using Store Sets. ISCA 1998: 142-153 | |
| 1997 | ||
| 13 | Joel S. Emer, Nicholas C. Gloy: A Language for Describing Predictors and Its Application to Automatic Synthesis. ISCA 1997: 304-314 | |
| 12 | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen: Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Trans. Comput. Syst. 15(3): 322-354 (1997) | |
| 1996 | ||
| 11 | Brad Calder, Dirk Grunwald, Joel S. Emer: Predictive Sequential Associative Cache. HPCA 1996: 244-253 | |
| 10 | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA 1996: 191-202 | |
| 9 | Joel S. Emer: Incremental Versus Revolutionary Research. ACM Comput. Surv. 28(4es): 27 (1996) | |
| 1995 | ||
| 8 | Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer: Instruction Fetching: Coping with Code Bloat. ISCA 1995: 345-356 | |
| 7 | Brad Calder, Dirk Grunwald, Joel S. Emer: A system level perspective on branch architecture performance. MICRO 1995: 199-206 | |
| 1989 | ||
| 6 | Joel S. Emer: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989. ACM Press 1989 | |
| 5 | K. K. Ramakrishnan, Joel S. Emer: Performance Analysis of Mass Storage Service Alternatives for Distributed Systems. IEEE Trans. Software Eng. 15(2): 120-133 (1989) | |
| 1988 | ||
| 4 | Joel S. Emer, K. K. Ramakrishnan: Performance Considerations for Distributed Services: A Case Study: Mass Storage. ICDCS 1988: 289-297 | |
| 1986 | ||
| 3 | Joel S. Emer, K. K. Ramakrishnan: Design analysis of a heterogeneous distributed system. ACM SIGOPS European Workshop 1986 | |
| 1985 | ||
| 2 | Douglas W. Clark, Joel S. Emer: Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement ACM Trans. Comput. Syst. 3(1): 31-62 (1985) | |
| 1984 | ||
| 1 | Joel S. Emer, Douglas W. Clark: A Characterization of Processor Performance in the VAX-11/780. ISCA 1984: 301-310 | |
Colors in the list of coauthors
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