Emmanuelle Encrenaz
List of publications from the DBLP Bibliography Server - FAQ
| 2009 | ||
|---|---|---|
| 16 | Emmanuelle Encrenaz, Alain Finkel: Automatic Verification of Counter Systems With Ranking Function. Electr. Notes Theor. Comput. Sci. 239: 85-103 (2009) | |
| 15 | Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Timed verification of the generic architecture of a memory circuit using parametric timed automata. Formal Methods in System Design 34(1): 59-81 (2009) | |
| 2008 | ||
| 14 | Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz: A tool for automatic detection of deadlock in wormhole networks on chip. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) | |
| 13 | Emmanuelle Encrenaz, Laurent Fribourg: Time Separation of Events: An Inverse Method. Electr. Notes Theor. Comput. Sci. 209: 135-148 (2008) | |
| 12 | Étienne André, Thomas Chatain, Laurent Fribourg, Emmanuelle Encrenaz: An Inverse Method for Parametric Timed Automata. Electr. Notes Theor. Comput. Sci. 223: 29-46 (2008) | |
| 2007 | ||
| 11 | Cécile Braunstein, Emmanuelle Encrenaz: Using CTL formulae as component abstraction in a design and verification flow. ACSD 2007: 80-89 | |
| 10 | Cécile Braunstein, Emmanuelle Encrenaz: CTL-property Transformations along an Incremental Design Process. STTT 9(1): 77-88 (2007) | |
| 2006 | ||
| 9 | Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. FORMATS 2006: 113-127 | |
| 8 | Cécile Braunstein, Emmanuelle Encrenaz: Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter. IEEE International Workshop on Rapid System Prototyping 2006: 103-109 | |
| 2005 | ||
| 7 | Cécile Braunstein, Emmanuelle Encrenaz: CTL-Property Transformations Along an Incremental Design Process. Electr. Notes Theor. Comput. Sci. 128(6): 263-278 (2005) | |
| 2003 | ||
| 6 | Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou Desbarbieux: Design Validation of ZCSP with SPIN. ACSD 2003: 102-110 | |
| 5 | Cédric Roux, Emmanuelle Encrenaz: CTL May Be Ambiguous When Model Checking Moore Machines. CHARME 2003: 164-169 | |
| 2002 | ||
| 4 | Jean-Michel Couvreur, Emmanuelle Encrenaz, Emmanuel Paviot-Adet, Denis Poitrenaud, Pierre-André Wacrenier: Data Decision Diagrams for Petri Net Analysis. ICATPN 2002: 101-120 | |
| 1998 | ||
| 3 | Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa: Modular model checking of VLSI designs described in VHDL. Computers and Their Applications 1998: 368-371 | |
| 1996 | ||
| 2 | Rajesh K. Bawa, Emmanuelle Encrenaz: A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis. FTRTFT 1996: 471-474 | |
| 1995 | ||
| 1 | Emmanuelle Encrenaz: A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking. CHARME 1995: 328-342 | |
| 1 | Étienne André | [12] |
| 2 | Rajesh K. Bawa | [2] [3] |
| 3 | Vincent Beaudenon | [6] |
| 4 | Cécile Braunstein | [7] [8] [10] [11] |
| 5 | Thomas Chatain | [12] |
| 6 | Remy Chevallier | [9] [15] |
| 7 | Jean-Michel Couvreur | [4] |
| 8 | Jean Lou Desbarbieux | [6] [14] |
| 9 | Alain Finkel | [16] |
| 10 | Laurent Fribourg | [9] [12] [13] [15] |
| 11 | Michel Minoux | [3] |
| 12 | Emmanuel Paviot-Adet | [4] |
| 13 | Denis Poitrenaud | [4] |
| 14 | Fahim Rahim-Sarwary | [3] |
| 15 | Cédric Roux | [5] |
| 16 | Sami Taktak | [14] |
| 17 | Pierre-André Wacrenier | [4] |
| 18 | Weiwen Xu | [9] [15] |