Stijn Eyerman Vis

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*2009
11EEStijn Eyerman, Lieven Eeckhout: Per-thread cycle accounting in SMT processors. ASPLOS 2009: 133-144
10EEKenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout: MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. HiPEAC 2009: 110-124
9EEStijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27(2): (2009)
8EEStijn Eyerman, Lieven Eeckhout: Memory-level parallelism aware fetch policies for simultaneous multithreading processors. TACO 6(1): (2009)
2008
7EEStijn Eyerman, Lieven Eeckhout, James E. Smith: Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC 2008: 114-129
2007
6EEStijn Eyerman, Lieven Eeckhout: A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. HPCA 2007: 240-249
5EEStijn Eyerman, Lieven Eeckhout, James E. Smith: Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT 2007: 406
4EEStijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro 27(1): 84-93 (2007)
2006
3EEStijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A performance counter architecture for computing accurate CPI components. ASPLOS 2006: 175-184
2EEStijn Eyerman, Lieven Eeckhout, Koen De Bosschere: Efficient design space exploration of high performance embedded out-of-order processors. DATE 2006: 351-356
1EEStijn Eyerman, James E. Smith, Lieven Eeckhout: Characterizing the branch misprediction penalty. ISPASS 2006: 48-58

Coauthor Index

1Koen De Bosschere (Koenraad De Bosschere) [2]
2Kenzo Van Craeynest [10]
3Lieven Eeckhout [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
4Tejas Karkhanis [3] [4] [9]
5James E. Smith [1] [3] [4] [5] [7] [9]

Copyright © Fri Jul 3 18:20:30 2009 by Michael Ley (ley@uni-trier.de)