Görschwin Fey

	2011
64		Görschwin Fey: Orchestrated multi-level information flow analysis to understand SoCs. DAC 2011: 284-285
63		Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler: Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422
62		Mehdi Dehbashi, André Sülflow, Görschwin Fey: Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486
61		Alexander Finder, André Sülflow, Görschwin Fey: Latency Analysis for Sequential Circuits. European Test Symposium 2011: 129-134
60		Görschwin Fey: Assessing System Vulnerability Using Formal Verification Techniques. MEMICS 2011: 47-56
59		Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1239-1252 (2011)
	2010
58		Rolf Drechsler, Görschwin Fey: Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4
57		Stefan Frehse, Görschwin Fey, Rolf Drechsler: A better-than-worst-case robustness measure. DDECS 2010: 78-83
56		Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231
55		Alexander Finder, Görschwin Fey: Evaluating Debugging Algorithms from a Qualitative Perspective. FDL 2010: 37-42
54		Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler: Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761
53		André Sülflow, Görschwin Fey, Rolf Drechsler: Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644
52		Görschwin Fey, André Sülflow, Rolf Drechsler: Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8
51		Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler: MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electronic Testing 26(3): 307-322 (2010)
50		Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it - Information Technology 52(4): 216-223 (2010)
	2009
49		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille: Test Pattern Generation using Boolean Proof Engines. Springer 2009: I-XII, 1-192
48		Görschwin Fey: Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium 2009: 313-316
47		Görschwin Fey, André Sülflow, Rolf Drechsler: Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195
46		André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331
45		Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90
44		André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17
43		André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler: Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303
42		Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Advanced verification by automatic property generation. IET Computers & Digital Techniques 3(4): 338-353 (2009)
41		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille: Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it - Information Technology 51(2): 102-111 (2009)
	2008
40		Görschwin Fey, Rolf Drechsler: Robustness and usability in modern design flows. Springer 2008: I-XIII, 1-166
39		André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82
38		Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548
37		Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549
36		Görschwin Fey, Rolf Drechsler: A Basis for Formal Robustness Checking. ISQED 2008: 784-789
35		Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008)
34		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
33		Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the construction of small fully testable circuits with low depth. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008)
	2007
32		Daniel Tille, Görschwin Fey, Rolf Drechsler: Instance Generation for SAT-based ATPG. DDECS 2007: 153-156
31		Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569
30		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674
29		Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
28		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
27		Görschwin Fey, Tim Warode, Rolf Drechsler: Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76
26		Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
	2006
25		Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
24		Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
23		Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64
22		Görschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25
21		Rolf Drechsler, Görschwin Fey: Automatic Test Pattern Generation. SFM 2006: 30-55
20		Rolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242
19		Görschwin Fey, Rolf Drechsler: Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006)
18		Görschwin Fey: Increasing robustness and usability of circuit design tools by using formal techniques. Universität Bremen 2006: I-VIII, 1-164
	2005
17		Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler: Advanced BDD optimization. Springer 2005: I-X, 1-222
16		Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
15		Junhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191
14		Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
13		Sebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255
12		Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
	2004
11		Görschwin Fey, Rolf Drechsler: Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643
10		Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. DATE 2004: 162-167
9		Görschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172
8		Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler: Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207
7		Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
6		Rolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)
	2003
5		Rolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83
4		Junhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293
3		Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
2		Görschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366
1		Görschwin Fey, Rolf Drechsler: Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51-

Coauthor Index

1	Bijan Alizadeh	[54]
2	Gerhard Angst	[37]
3	Anna Bernasconi	[31] [33]
4	Roderick Bloem (Roderick Paul Bloem)	[23] [35] [39]
5	Cécile Braunstein	[46]
6	Maciej J. Ciesielski	[7]
7	Valentina Ciriani	[31] [33]
8	Mehdi Dehbashi	[62]
9	Nicole Drechsler	[8]
10	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [49] [50] [51] [52] [53] [54] [56] [57] [58] [59] [63]
11	Rüdiger Ebendt	[17]
12	Stephan Eggersglüß	[26] [28] [29] [30] [34] [41] [49] [51]
13	Alexander Finder	[55] [61]
14	Stefan Frehse	[45] [50] [56] [57] [59]
15	Martin Freibothe	[63]
16	Masahiro Fujita	[54]
17	Christian Genz	[14]
18	Andreas Glowatz	[12] [28] [29] [34] [51]
19	Daniel Große	[3] [14] [24] [26] [44]
20	Finn Haedicke	[54]
21	Friedrich Hapke	[12] [28] [29] [34] [51]
22	Mario Hilgemeier	[8]
23	Sebastian Kinder	[2] [13] [20]
24	Thomas Klotz	[38] [42]
25	Ulrich Kühne	[44] [46] [63]
26	Lothar Linhard	[37]
27	Marc Messing	[37]
28	Frank Rogin	[38] [42]
29	Steffen Rülke	[38] [42]
30	Sean Safarpour	[16] [25]
31	Jürgen Schlöffel	[12] [28] [29] [34] [41] [51]
32	Junhao Shi	[4] [5] [6] [9] [12] [15] [22]
33	Mathias Soeken	[63]
34	Stefan Staber	[23] [35]
35	Dominik Stoffel	[10]
36	André Sülflow	[39] [43] [44] [45] [46] [47] [50] [52] [53] [56] [59] [61] [62]
37	Daniel Tille	[29] [32] [34] [41] [49]
38	Hans-Joachim Trylus	[10]
39	Andreas G. Veneris	[16] [25]
40	Tim Warode	[27]
41	Robert Wille	[26] [37] [43]
42	Klaus Winkelmann	[10]

Colors in the list of coauthors

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