Görschwin Fey

	2009
42		Görschwin Fey, André Sülflow, Rolf Drechsler: Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195
41		André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331
40		Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90
39		André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17
38		André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler: Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303
	2008
37		André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82
36		Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548
35		Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549
34		Görschwin Fey, Rolf Drechsler: A Basis for Formal Robustness Checking. ISQED 2008: 784-789
33		Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008)
32		Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)
31		Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the construction of small fully testable circuits with low depth. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008)
	2007
30		Daniel Tille, Görschwin Fey, Rolf Drechsler: Instance Generation for SAT-based ATPG. DDECS 2007: 153-156
29		Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569
28		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674
27		Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
26		Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187
25		Görschwin Fey, Tim Warode, Rolf Drechsler: Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76
24		Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
	2006
23		Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
22		Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226
21		Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64
20		Görschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25
19		Rolf Drechsler, Görschwin Fey: Automatic Test Pattern Generation. SFM 2006: 30-55
18		Rolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242
17		Görschwin Fey, Rolf Drechsler: Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006)
	2005
16		Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
15		Junhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191
14		Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260
13		Sebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255
12		Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217
	2004
11		Görschwin Fey, Rolf Drechsler: Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643
10		Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. DATE 2004: 162-167
9		Görschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172
8		Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler: Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207
7		Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240
6		Rolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)
	2003
5		Rolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83
4		Junhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293
3		Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286
2		Görschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366
1		Görschwin Fey, Rolf Drechsler: Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51-

Coauthor Index

1	Gerhard Angst	[35]
2	Anna Bernasconi	[29] [31]
3	Roderick Bloem	[21] [33] [37]
4	Cécile Braunstein	[41]
5	Maciej J. Ciesielski	[7]
6	Valentina Ciriani	[29] [31]
7	Nicole Drechsler	[8]
8	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42]
9	Stephan Eggersglüß	[24] [26] [27] [28] [32]
10	Stefan Frehse	[40]
11	Christian Genz	[14]
12	Andreas Glowatz	[12] [26] [27] [32]
13	Daniel Große	[3] [14] [22] [24] [39]
14	Friedrich Hapke	[12] [26] [27] [32]
15	Mario Hilgemeier	[8]
16	Sebastian Kinder	[2] [13] [18]
17	Thomas Klotz	[36]
18	Ulrich Kühne	[39] [41]
19	Lothar Linhard	[35]
20	Marc Messing	[35]
21	Frank Rogin	[36]
22	Steffen Rülke	[36]
23	Sean Safarpour	[16] [23]
24	Jürgen Schlöffel	[12] [26] [27] [32]
25	Junhao Shi	[4] [5] [6] [9] [12] [15] [20]
26	Stefan Staber	[21] [33]
27	Dominik Stoffel	[10]
28	André Sülflow	[37] [38] [39] [40] [41] [42]
29	Daniel Tille	[27] [30] [32]
30	Hans-Joachim Trylus	[10]
31	Andreas G. Veneris	[16] [23]
32	Tim Warode	[25]
33	Robert Wille	[24] [35] [38]
34	Klaus Winkelmann	[10]

Colors in the list of coauthors