 | 2009 |
|---|
| 15 |       | Igor Lemberski,
Petr Fiser:
Asynchronous two-level logic of reduced cost.
DDECS 2009: 68-73 |
| 2008 |
|---|
| 14 | | Petr Fiser,
Pemysl Rucký,
Irena Vanová:
Fast Boolean Minimizer for Completely Specified Functions.
DDECS 2008: 122-127 |
| 13 | | Petr Fiser,
Pavel Kubalík,
Hana Kubatova:
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.
DSD 2008: 96-99 |
| 12 | | Petr Fiser,
Hana Kubatova:
Column-matching based mixed-mode test pattern generator design technique for BIST.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 340-350 (2008) |
| 2007 |
|---|
| 11 | | Petr Fiser:
Pseudo-Random Pattern Generator Design for Column-Matching BIST.
DSD 2007: 657-663 |
| 2006 |
|---|
| 10 |  | Petr Fiser,
Hana Kubatova:
Multiple-Vector Column-Matching BIST Design Method.
DDECS 2006: 268-273 |
| 9 | | Petr Fiser,
Hana Kubatova:
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.
DSD 2006: 369-376 |
| 8 | | Pavel Kubalík,
Petr Fiser,
Hana Kubatova:
Fault Tolerant System Design Method Based on Self-Checking Circuits.
IOLTS 2006: 185-186 |
| 2004 |
|---|
| 7 | | Petr Fiser,
Hana Kubatova:
Boolean Minimizer FC-Min: Coverage Finding Process.
DSD 2004: 152-159 |
| 6 | | Petr Fiser,
Hana Kubatova:
Survey of the Algorithms in the Column-Matching BIST Method.
IOLTS 2004: 181 |
| 2003 |
|---|
| 5 | | Petr Fiser,
Jan Hlavicka,
Hana Kubatova:
FC-Min: A Fast Multi-Output Boolean Minimizer.
DSD 2003: 451-454 |
| 4 | | Petr Fiser,
Jan Hlavicka:
BOOM - A Heuristic Boolean Minimizer.
Computers and Artificial Intelligence 22(1): (2003) |
| 2002 |
|---|
| 3 | | Jan Hlavicka,
Petr Fiser:
Minimization and Partitioning Method Reducing Input Sets.
DELTA 2002: 434-436 |
| 2001 |
|---|
| 2 | | Petr Fiser,
Jan Hlavicka:
On the Use of Mutations in Boolean Minimization.
DSD 2001: 300-309 |
| 1 | | Jan Hlavicka,
Petr Fiser:
BOOM - A Heuristic Boolean Minimizer.
ICCAD 2001: 439-442 |
