 | 2008 |
|---|
| 9 |       | Dorit Baras,
Laurent Fournier,
Avi Ziv:
Automatic Boosting of Cross-Product Coverage Using Bayesian Networks.
Haifa Verification Conference 2008: 53-67 |
| 2007 |
|---|
| 8 | | Allon Adir,
Sigal Asaf,
Laurent Fournier,
Itai Jaeger,
Ofer Peled:
A Framework for the Validation of Processor Architecture Compliance.
DAC 2007: 902-905 |
| 7 | | Laurent Fournier,
Avi Ziv:
Using Virtual Coverage to Hit Hard-To-Reach Events.
Haifa Verification Conference 2007: 104-119 |
| 2006 |
|---|
| 6 | | Hezi Azatchi,
Laurent Fournier,
Eitan Marcus,
Shmuel Ur,
Avi Ziv,
Keren Zohar:
Advanced Analysis Techniques for Cross-Product Coverage.
IEEE Trans. Computers 55(11): 1367-1379 (2006) |
| 2004 |
|---|
| 5 | | Eyal Bin,
Laurent Fournier:
Micro-Architecture Verification for Microprocessors.
MTV 2004: 112-113 |
| 4 | | Allon Adir,
Eli Almog,
Laurent Fournier,
Eitan Marcus,
Michal Rimon,
Michael Vinov,
Avi Ziv:
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Design & Test of Computers 21(2): 84-93 (2004) |
| 2003 |
|---|
| 3 |  | Avi Ziv,
Laurent Fournier:
Solving the generalized mask constraint for test generation of binary floating point add operation.
Theor. Comput. Sci. 291(2): 183-201 (2003) |
| 1999 |
|---|
| 2 | | Laurent Fournier,
Anatoly Koyfman,
Moshe Levinger:
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture.
DAC 1999: 189-194 |
| 1 | | Laurent Fournier,
Yaron Arbetman,
Moshe Levinger:
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family.
DATE 1999: 434-441 |
