Eby G. Friedman

	2009
140		Renatas Jakushokas, Eby G. Friedman: Simultaneous shield and repeater insertion. ACM Great Lakes Symposium on VLSI 2009: 15-20
139		Eby G. Friedman: Design challenges in high performance three-dimensional circuits. ACM Great Lakes Symposium on VLSI 2009: 281-282
138		Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290
137		Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Contact merging algorithm for efficient substrate noise analysis in large scale circuits. ACM Great Lakes Symposium on VLSI 2009: 9-14
136		Jonathan Rosenfeld, Eby G. Friedman: On-chip DC-DC converters for three-dimensional ICs. ISQED 2009: 759-764
	2008
135		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Equivalent rise time for resonance in power/ground noise estimation. ISCAS 2008: 2422-2425
134		Guoqing Chen, Eby G. Friedman: Transient simulation of on-chip transmission lines via exact pole extraction. ISCAS 2008: 2757-2760
133		Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Input port reduction for efficient substrate extraction in large scale IC's. ISCAS 2008: 376-379
132		Ioannis Savidis, Eby G. Friedman: Electrical modeling and characterization of 3-D vias. ISCAS 2008: 784-787
131		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. ISQED 2008: 261-266
130		Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
129		Alexander Lavzin, Mücahit Kozak, Eby G. Friedman: A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. SoCC 2008: 267-270
128		Selcuk Kose, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman: Pseudo-random clocking to enhance signal integrity. SoCC 2008: 47-50
127		Mikhail Popovich, Eby G. Friedman: Nanoscale on-chip decoupling capacitors. SoCC 2008: 51-54
126		Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs. IEEE Trans. VLSI Syst. 16(12): 1717-1721 (2008)
125		Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman: Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. VLSI Syst. 16(7): 894-907 (2008)
124		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. VLSI Syst. 16(7): 908-921 (2008)
123		Vasilis F. Pavlidis, Eby G. Friedman: Timing-driven via placement heuristics for three-dimensional ICs. Integration 41(4): 489-508 (2008)
	2007
122		Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. ICCAD 2007: 811-816
121		Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Substrate Noise Reduction Based On Noise Aware Cell Design. ISCAS 2007: 3227-3230
120		Jonathan Rosenfeld, Eby G. Friedman: Quasi-Resonant Interconnects: A Low Power Design Methodology. ISCAS 2007: 641-644
119		Vasilis F. Pavlidis, Eby G. Friedman: 3-D Topologies for Networks-on-Chip. IEEE Trans. VLSI Syst. 15(10): 1081-1090 (2007)
118		Jonathan Rosenfeld, Eby G. Friedman: Design Methodology for Global Resonant H-Tree Clock Distribution Networks. IEEE Trans. VLSI Syst. 15(2): 135-148 (2007)
117		Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman: Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1114-1125 (2007)
116		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman: Predictions of CMOS compatible on-chip optical interconnect. Integration 40(4): 434-446 (2007)
115		Magdy A. El-Moursy, Eby G. Friedman: Wire shaping of RLC interconnects. Integration 40(4): 461-472 (2007)
	2006
114		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu: Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179
113		Jonathan Rosenfeld, Eby G. Friedman: Sensitivity evaluation of global resonant H-tree clock distribution networks. ACM Great Lakes Symposium on VLSI 2006: 192-197
112		Jonathan Rosenfeld, Eby G. Friedman: Design methodology for global resonant H-tree clock distribution networks. ISCAS 2006
111		Guoqing Chen, Eby G. Friedman: Effective capacitance of RLC loads for estimating short-circuit power. ISCAS 2006
110		Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman: On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006
109		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire tapering for minimum power dissipation in RLC interconnects. ISCAS 2006
108		Vasilis F. Pavlidis, Eby G. Friedman: Via placement for minimum interconnect delay in three-dimensional (3D) circuits. ISCAS 2006
107		Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar: Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. ISQED 2006: 159-164
106		Guoqing Chen, Eby G. Friedman: Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans. VLSI Syst. 14(2): 161-172 (2006)
105		Mikhail Popovich, Eby G. Friedman: Decoupling capacitors for multi-voltage power distribution systems. IEEE Trans. VLSI Syst. 14(3): 217-228 (2006)
104		Junmou Zhang, Eby G. Friedman: Crosstalk modeling for coupled RLC interconnects with application to shield insertion. IEEE Trans. VLSI Syst. 14(6): 641-646 (2006)
103		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Sizing CMOS inverters with Miller Effect and Threshold voltage Variations. Journal of Circuits, Systems, and Computers 15(3): 437-454 (2006)
	2005
102		Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7
101		Vasilis F. Pavlidis, Eby G. Friedman: Interconnect delay minimization through interlayer via placement in 3-D ICs. ACM Great Lakes Symposium on VLSI 2005: 20-25
100		Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra: Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467
99		Guoqing Chen, Eby G. Friedman: Low power repeaters driving RLC interconnects with delay and bandwidth constraints. ISCAS (1) 2005: 596-599
98		Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman: Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. ISCAS (1) 2005: 612-615
97		Mikhail Popovich, Eby G. Friedman: Noise coupling in multi-voltage power distribution systems with decoupling capacitors. ISCAS (1) 2005: 620-623
96		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) 2005: 2514-2517
95		Guoqing Chen, Eby G. Friedman: A Fourier series-based RLC interconnect model for periodic signals. ISCAS (4) 2005: 4126-4129
94		Mikhail Popovich, Eby G. Friedman: Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. ISQED 2005: 334-339
93		Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Predictions of CMOS compatible on-chip optical interconnect. SLIP 2005: 13-20
92		Magdy A. El-Moursy, Eby G. Friedman: Shielding effect of on-chip interconnect inductance. IEEE Trans. VLSI Syst. 13(3): 396-400 (2005)
91		Magdy A. El-Moursy, Eby G. Friedman: Exponentially tapered H-tree clock distribution networks. IEEE Trans. VLSI Syst. 13(8): 971-975 (2005)
90		Guoqing Chen, Eby G. Friedman: An RLC interconnect model based on fourier analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 170-183 (2005)
89		Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra: Monolithic voltage conversion in low-voltage CMOS technologies. Microelectronics Journal 36(9): 863-867 (2005)
	2004
88		Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman: A low power thyristor-based CMOS programmable delay element. ISCAS (1) 2004: 769-772
87		Volkan Kursun, Eby G. Friedman: Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. ISCAS (2) 2004: 417-420
86		Junmou Zhang, Eby G. Friedman: Decoupling technique and crosstalk analysis for coupled RLC interconnects. ISCAS (2) 2004: 521-524
85		Junmou Zhang, Eby G. Friedman: Effect of shield insertion on reducing crosstalk noise between coupled interconnects. ISCAS (2) 2004: 529-532
84		Magdy A. El-Moursy, Eby G. Friedman: Exponentially tapered H-tree clock distribution networks. ISCAS (2) 2004: 601-604
83		Volkan Kursun, Eby G. Friedman: Forward body biased keeper for enhanced noise immunity in domino logic circuits. ISCAS (2) 2004: 917-920
82		Mücahit Kozak, Eby G. Friedman: Design and simulation of Fractional-N PLL frequency synthesizers. ISCAS (4) 2004: 780-783
81		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Low power flexible Rake receivers for WCDMA. ISCAS (4) 2004: 97-100
80		Volkan Kursun, Eby G. Friedman: Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. ISQED 2004: 104-109
79		Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521
78		Dimitrios Velenis, Eby G. Friedman: Buffer Sizing for Crosstalk Induced Delay Uncertainty. PATMOS 2004: 750-759
77		Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman: Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. VLSI Syst. 12(1): 67-78 (2004)
76		Andrey V. Mezhiba, Eby G. Friedman: Impedance characteristics of power distribution grids in nanoscale integrated circuits. IEEE Trans. VLSI Syst. 12(11): 1148-1155 (2004)
75		Magdy A. El-Moursy, Eby G. Friedman: Power characteristics of inductive interconnect. IEEE Trans. VLSI Syst. 12(12): 1295-1306 (2004)
74		Andrey V. Mezhiba, Eby G. Friedman: Scaling trends of on-chip power distribution noise. IEEE Trans. VLSI Syst. 12(4): 386-394 (2004)
73		Volkan Kursun, Eby G. Friedman: Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. IEEE Trans. VLSI Syst. 12(5): 485-496 (2004)
72		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire sizing of RLC interconnect with repeaters . Integration 38(2): 205-225 (2004)
71		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Complex +/-1 Multiplier Based on Signed-Binary Transformations. VLSI Signal Processing 38(1): 13-24 (2004)
	2003
70		Magdy A. El-Moursy, Eby G. Friedman: Shielding effect of on-chip interconnect inductance. ACM Great Lakes Symposium on VLSI 2003: 165-170
69		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Orthogonal code generator for 3G wireless transceivers. ACM Great Lakes Symposium on VLSI 2003: 229-232
68		Magdy A. El-Moursy, Eby G. Friedman: Optimum wire sizing of RLC interconnect with repeaters. ACM Great Lakes Symposium on VLSI 2003: 27-32
67		Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075
66		Magdy A. El-Moursy, Eby G. Friedman: Inductive interconnect width optimization for low power. ISCAS (5) 2003: 273-276
65		Andrey V. Mezhiba, Eby G. Friedman: Electrical characteristics of multi-layer power distribution grids. ISCAS (5) 2003: 473-476
64		Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman: Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279-
63		Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman: Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. IWSOC 2003: 70-75
62		David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer 36(12): 49-58 (2003)
61		Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman: Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. VLSI Syst. 11(3): 514-522 (2003)
60		Volkan Kursun, Eby G. Friedman: Domino logic with variable threshold voltage keeper. IEEE Trans. VLSI Syst. 11(6): 1080-1093 (2003)
59		Yehea I. Ismail, Eby G. Friedman: On the Extraction of On-Chip Inductance. Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003)
	2002
58		Andrey V. Mezhiba, Eby G. Friedman: Properties of on-chip inductive current loops. ACM Great Lakes Symposium on VLSI 2002: 12-17
57		Volkan Kursun, Eby G. Friedman: Low swing dual threshold voltage domino logic. ACM Great Lakes Symposium on VLSI 2002: 47-52
56		Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum: Efficient implementation of a complex ±1 multiplier. ACM Great Lakes Symposium on VLSI 2002: 83-88
55		Andrey V. Mezhiba, Eby G. Friedman: Inductance/area/resistance tradeoffs in high performance power distribution grids. ISCAS (1) 2002: 101-104
54		Weize Xu, Eby G. Friedman: A substrate noise circuit for accurately testing mixed-signal ICs. ISCAS (1) 2002: 145-148
53		Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev: Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360
52		Andrey V. Mezhiba, Eby G. Friedman: Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. ISQED 2002: 316-321
51		Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman: Managing static leakage energy in microprocessor functional units. MICRO 2002: 321-332
50		Andrey V. Mezhiba, Eby G. Friedman: Scaling trends of on-chip Power distribution noise. SLIP 2002: 47-53
49		Kevin T. Tang, Eby G. Friedman: Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans. VLSI Syst. 10(4): 487-493 (2002)
48		Andrey V. Mezhiba, Eby G. Friedman: Inductive properties of high-performance power distribution grids. IEEE Trans. VLSI Syst. 10(6): 762-776 (2002)
47		Yehea I. Ismail, Eby G. Friedman: DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002)
46		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)
45		Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman: Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002)
44		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Journal of Circuits, Systems, and Computers 11(3): 305- (2002)
	2001
43		Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou: A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425
42		Kevin T. Tang, Eby G. Friedman: Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. ISCAS (5) 2001: 463-466
41		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. VLSI Syst. 9(6): 963-973 (2001)
	2000
40		Kevin T. Tang, Eby G. Friedman: Noise estimation due to signal activity for capacitively coupled CMOS logic gates. ACM Great Lakes Symposium on VLSI 2000: 171-176
39		Radu M. Secareanu, Eby G. Friedman: Transparent repeaters. ACM Great Lakes Symposium on VLSI 2000: 63-66
38		Yehea I. Ismail, Eby G. Friedman: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. VLSI Syst. 8(2): 195-206 (2000)
37		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore delay for RLC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000)
36		Kevin T. Tang, Eby G. Friedman: Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. Integration 29(2): 131-165 (2000)
	1999
35		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236
34		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720
33		Yehea I. Ismail, Eby G. Friedman: Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC 1999: 721-724
32		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649
31		Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman: Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317
30		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59
29		Ivan S. Kourtev, Eby G. Friedman: Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243
28		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424
27		Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner: A universal CMOS voltage interface circuit. ISCAS (1) 1999: 242-245
26		Kevin T. Tang, Eby G. Friedman: Peak noise prediction in loosely coupled interconnect [VLSI circuits]. ISCAS (1) 1999: 541-544
25		Radu M. Secareanu, Eby G. Friedman: A high precision CMOS current mirror/divider. ISCAS (2) 1999: 314-317
24		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193
23		Yehea I. Ismail, Eby G. Friedman: Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) 1999: 404-407
22		Kevin T. Tang, Eby G. Friedman: Interconnect coupling noise in CMOS VLSI circuits. ISPD 1999: 48-53
21		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. VLSI Syst. 7(4): 442-449 (1999)
	1998
20		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565
19		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44
18		Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142
	1997
17		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997)
16		Eby G. Friedman: High Performance Clock Distribution Networks. VLSI Signal Processing 16(2-3): 113-116 (1997)
15		José Luis Neves, Eby G. Friedman: Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. VLSI Signal Processing 16(2-3): 149-161 (1997)
14		Kris Gaj, Eby G. Friedman, Marc J. Feldman: Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. VLSI Signal Processing 16(2-3): 247-276 (1997)
	1996
13		José Luis Neves, Eby G. Friedman: Optimal Clock Skew Scheduling Tolerant to Process Variations. DAC 1996: 623-628
12		José Luis Neves, Eby G. Friedman: Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. IEEE Trans. VLSI Syst. 4(2): 286-291 (1996)
	1995
11		José Luis Neves, Eby G. Friedman: Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. ISCAS 1995: 1576-1579
10		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751
9		Brian S. Cherkauer, Eby G. Friedman: A unified design methodology for CMOS tapered buffers. IEEE Trans. VLSI Syst. 3(1): 99-111 (1995)
	1994
8		Tolga Soyata, Eby G. Friedman: Retiming with non-zero clock skew, variable register, and interconnect delay. ICCAD 1994: 234-241
7		Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan: Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. ISCAS 1994: 1-6
6		Brian S. Cherkauer, Eby G. Friedman: Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. ISCAS 1994: 111-114
5		José Luis Neves, Eby G. Friedman: Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. ISCAS 1994: 175-178
4		Brian S. Cherkauer, Eby G. Friedman: Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. IEEE Trans. VLSI Syst. 2(1): 100-114 (1994)
	1993
3		Eby G. Friedman: Clock Distribution Design in VLSI Circuits. An Overview. ISCAS 1993: 1475-1478
2		Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.: Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486
1		Brian S. Cherkauer, Eby G. Friedman: The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. ISCAS 1993: 2110-2113

Coauthor Index

1	V. Adler	[45]
2	David H. Albonesi	[51] [62] [93] [96] [116]
3	David J. Allstot	[7]
4	Boris D. Andreev	[56] [63] [69] [71] [81] [103]
5	F. Baez	[45]
6	Rajeev Balasubramonian	[62]
7	S. K. Banerjee	[98]
8	Juan Becerra	[27] [31] [77]
9	Pradip Bose	[62]
10	Cathie Burke	[77]
11	Alper Buyuktosunoglu	[62]
12	Guoqing Chen	[90] [93] [95] [96] [99] [106] [111] [116] [134]
13	Hui Chen	[93] [96] [116]
14	Brian S. Cherkauer	[1] [4] [6] [9]
15	Peter W. Cook	[62]
16	Simon R. Cooper	[88]
17	Ali Dasdan	[107] [117]
18	Vivek De	[61] [64] [79] [89] [100]
19	Steven G. Dropsho (Steve Dropsho)	[51] [62]
20	Sandhya Dwarkadas	[51] [62]
21	Magdy A. El-Moursy	[66] [68] [70] [72] [75] [84] [91] [92] [109] [115]
22	Philippe M. Fauchet	[93] [96] [116]
23	Marc J. Feldman	[14]
24	Francisco V. Fernández (Francisco Vidal Fernández Fernández)	[98]
25	Kris Gaj	[14]
26	Ran Ginosar	[130] [138]
27	Robert M. Guidash	[88]
28	Erik P. Harris	[7]
29	Olin L. Hartin	[98] [121] [122] [126] [131] [133] [135] [137]
30	Mikhail Haurylau	[93] [96] [116]
31	Michael C. Huang	[62]
32	Zeljko Ignjatovic	[128]
33	Yehea I. Ismail	[18] [19] [20] [21] [23] [24] [28] [30] [33] [34] [37] [38] [41] [44] [47] [59]
34	Renatas Jakushokas	[133] [137] [140]
35	Sung-Mo Kang	[7]
36	Avinoam Kolodny	[102] [110] [114] [124] [125] [130] [138]
37	Selcuk Kose	[128]
38	Ivan S. Kourtev	[29] [31] [45] [53] [77]
39	Mücahit Kozak	[82] [129]
40	Kayhan Küçükçakar	[107] [117]
41	Volkan Kursun	[51] [57] [60] [61] [62] [64] [73] [79] [80] [83] [87] [89] [100]
42	Andrew R. LaPietra	[88]
43	Alexander Lavzin	[129]
44	Ami Litman	[53]
45	Xun Liu	[32] [35] [46]
46	Roy Mader	[53]
47	Grigorios Magklis	[62]
48	Michael W. Mattern	[88]
49	Andrey V. Mezhiba	[48] [50] [52] [55] [58] [65] [74] [76]
50	Arkadiy Morgenshtein	[130]
51	Christopher Morton	[31] [77]
52	James H. Mulligan Jr.	[2] [10] [17]
53	Siva Narendra	[64] [79] [100]
54	Siva G. Narendra	[61] [89]
55	Nicholas Nelson	[93] [96] [116]
56	José Luis Neves	[5] [11] [12] [13] [15] [18] [19] [20] [21] [24] [28] [30] [34] [37] [41] [44]
57	Marios C. Papaefthymiou	[32] [35] [43] [46] [67]
58	Vasilis F. Pavlidis	[101] [108] [119] [123]
59	Mikhail Popovich	[94] [97] [102] [105] [110] [114] [122] [124] [125] [126] [127]
60	Jonathan Rosenfeld	[112] [113] [118] [120] [136]
61	Emre Salman	[107] [117] [121] [128] [131] [133] [135] [137]
62	Ioannis Savidis	[132]
63	Gerhard Schrom	[100]
64	Stanley Schuster	[62]
65	Michael L. Scott	[62]
66	Scott Seabridge	[77]
67	Radu M. Secareanu	[25] [27] [31] [39] [77] [98] [114] [121] [122] [126] [131] [133] [135] [137]
68	Greg Semeraro	[62]
69	Michael Sotman	[102] [110] [114] [124] [125]
70	Tolga Soyata	[2] [8] [10] [17]
71	William Staub	[31] [77]
72	Kevin T. Tang	[22] [26] [36] [40] [42] [45] [49]
73	Feroze Taraporevala	[107] [117]
74	Thomas Tellier	[31] [77]
75	Edward L. Titlebaum	[56] [63] [69] [71] [81] [103]
76	Inna Vaisband	[138]
77	Dimitrios Velenis	[43] [45] [67] [78]
78	Eric A. Vittoz	[7]
79	Scott Warner	[27] [77]
80	Thomas E. Watrobski	[31] [77]
81	Weize Xu	[54]
82	Ran-Hong Yan	[7]
83	Junmou Zhang	[85] [86] [88] [104]

Colors in the list of coauthors