 | 2009 |
|---|
| 7 |       | Shinobu Fujita:
Nano-electronics challenge chip designers meet real nano-electronics in 2010s?
DATE 2009: 431-432 |
| 6 | | Deming Chen,
Russell Tessier,
Kaustav Banerjee,
Mojy C. Chian,
André DeHon,
Shinobu Fujita,
James Hutchby,
Steve Trimberger:
CMOS vs Nano: comrades or rivals?
FPGA 2009: 121-122 |
| 2008 |
|---|
| 5 | | Igor Loi,
Subhasish Mitra,
Thomas H. Lee,
Shinobu Fujita,
Luca Benini:
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.
ICCAD 2008: 598-602 |
| 4 | | Bipul Chandra Paul,
Shinobu Fujita,
Masaki Okajima:
ROM based logic (RBL) design: High-performance and low-power adders.
ISCAS 2008: 796-799 |
| 2007 |
|---|
| 3 | | Bipul C. Paul,
Shinobu Fujita,
Masaki Okajima,
Thomas Lee:
Prospect of ballistic CNFET in high performance applications: Modeling and analysis.
JETC 3(3): (2007) |
| 2006 |
|---|
| 2 | | Bipul C. Paul,
Shinobu Fujita,
Masaki Okajima,
Thomas Lee:
Modeling and analysis of circuit performance of ballistic CNFET.
DAC 2006: 717-722 |
| 1 | | Ryuji Ohba,
Daisuke Matsushita,
Koichi Muraoka,
Shinichi Yasuda,
Tetsufumi Tanamoto,
Ken Uchida,
Shinobu Fujita:
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.
ISVLSI 2006: 231-236 |
