Hidehiro Fujiwara

	2009
11		Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663
10		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300
9		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Dependable SRAM with 7T/14T Memory Cells. IEICE Transactions 92-C(4): 423-432 (2009)
	2008
8		Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102
7		Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008)
6		Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008)
	2007
5		Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112
4		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Transactions 90-A(12): 2695-2702 (2007)
3		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions 90-C(10): 1949-1956 (2007)
	2006
2		Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
1		Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006)

Coauthor Index

1	Yusuke Iguchi	[3] [4] [5] [6] [8] [9] [10] [11]
2	Hiroshi Kawaguchi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
3	Kentaro Kawakami	[1]
4	Shinji Mikami	[1]
5	Junichi Miyakoshi	[1] [2] [7]
6	Yasuhiro Morita	[1] [2] [3] [4] [5] [6] [7] [8]
7	Yuichiro Murachi	[2] [7]
8	Koji Nii	[1] [2] [3] [4] [5] [6] [7] [11]
9	Hiroki Noguchi	[1] [3] [4] [5] [6] [7] [8] [9] [10] [11]
10	Shunsuke Okumura	[6] [8] [9] [10] [11]
11	Masahiko Yoshimoto	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
12	Shusuke Yoshimoto	[11]