Wolfgang Günther

	2006
50		Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal Hypergraph Drawing for Improved Visibility. J. Graph Algorithms Appl. 10(2): 141-157 (2006)
	2005
49		Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. VLSI Design 2005: 433-438
48		Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1515-1529 (2005)
	2004
47		Thomas Eschbach, Wolfgang Günther, Bernd Becker: Orthogonal hypergraph routing for improved visibility. ACM Great Lakes Symposium on VLSI 2004: 385-388
46		Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Minimization of the expected path length in BDDs based on local changes. ASP-DAC 2004: 865-870
45		Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC 2004: 875-878
	2003
44		Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: Combination of Lower Bounds in Exact BDD Minimization. DATE 2003: 10758-10763
43		Thomas Eschbach, Wolfgang Günther, Bernd Becker: Cross Reduction for Orthogonal Circuit Visualization. VLSI 2003: 107-113
42		Wolfgang Günther, Rolf Drechsler: Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52(9): 1196-1209 (2003)
41		Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler: An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1657-1663 (2003)
40		Ilia Polian, Wolfgang Günther, Bernd Becker: Pattern-based verification of connections to intellectual property cores. Integration 35(1): 25-44 (2003)
39		Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive bi-partitioning of netlists for large number of partitions. Journal of Systems Architecture 49(12-15): 521-528 (2003)
	2002
38		Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst: Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD 2002: 38-44
37		Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker: Crossing Reduction by Windows Optimization. Graph Drawing 2002: 285-294
36		Wolfgang Günther, Rolf Drechsler: Minimization of free BDDs. Integration 32(1-2): 41-59 (2002)
35		Rolf Drechsler, Wolfgang Günther, Stefan Höreth: Minimization of Word-Level Decision Diagrams. Integration 33(1-2): 39-70 (2002)
	2001
34		Wolfgang Günther, Andreas Hett, Bernd Becker: Application of linearly transformed BDDs in sequential verification. ASP-DAC 2001: 91-96
33		Ilia Polian, Wolfgang Günther, Bernd Becker: Efficient Pattern-Based Verification of Connections to IP Cores . Asian Test Symposium 2001: 443-448
32		Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst: Level Assignment for Displaying Combinational Logic. DSD 2001: 148-151
31		Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther: Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61
30		Frank Schmiedle, Wolfgang Günther, Rolf Drechsler: Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL 2001: 299-304
29		Wolfgang Günther, Rolf Drechsler: Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design 2001: 173-178
28		Wolfgang Günther, Rolf Drechsler: Performance Driven Optimization for MUX based FPGAs. VLSI Design 2001: 311-316
27		Rolf Drechsler, Wolfgang Günther, Fabio Somenzi: Using lower bounds during dynamic BDD minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 51-57 (2001)
26		Rolf Drechsler, Wolfgang Günther: History-based dynamic BDD minimization. Integration 31(1): 51-63 (2001)
	2000
25		Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker: Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105
24		Wolfgang Günther, Rolf Drechsler: ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO 2000: 1130-1137
23		Rolf Drechsler, Wolfgang Günther, Bernd Becker: Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192
22		Wolfgang Günther, Rolf Drechsler: Improving EAs for Sequencing Problems. GECCO 2000: 175-180
21		Rolf Drechsler, Wolfgang Günther: Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO 2000: 513-518
20		Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor: k-Layer Straightline Crossing Minimization by Speeding Up Sifting. Graph Drawing 2000: 253-258
19		Wolfgang Günther, Rolf Drechsler, Stefan Höreth: Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD 2000: 383-388
18		Dragan Jankovic, Wolfgang Günther, Rolf Drechsler: Lower Bound Sifting for MDDs. ISMVL 2000: 193-198
17		Frank Schmiedle, Wolfgang Günther, Rolf Drechsler: Dynamic Re-Encoding During MDD Minimization. ISMVL 2000: 239-244
16		Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther: A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452
15		Rolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast exact minimization of BDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 384-389 (2000)
14		Wolfgang Günther, Rolf Drechsler: On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75(3): 119-125 (2000)
13		Wolfgang Günther, Rolf Drechsler: ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. Journal of Systems Architecture 46(14): 1321-1334 (2000)
	1999
12		Wolfgang Günther, Rolf Drechsler: Minimization of Free BDDs. ASP-DAC 1999: 323-326
11		Rolf Drechsler, Wolfgang Günther: Using Lower Bounds During Dynamic BDD Minimization. DAC 1999: 29-32
10		Rolf Drechsler, Wolfgang Günther: Generation of Optimal Universal Logic Modules. EUROMICRO 1999: 1080-1085
9		Nicole Drechsler, Wolfgang Günther, Rolf Drechsler: Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days 1999: 30-39
8		Wolfgang Günther, Rolf Drechsler: Efficient manipulation algorithms for linearly transformed BDDs. ICCAD 1999: 50-54
7		Wolfgang Günther, Rolf Drechsler: Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) 1999: 387-390
6		Wolfgang Günther, Rolf Drechsler: Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) 1999: 436-439
5		Rolf Drechsler, Wolfgang Günther: History-Based Dynamic Minimization During BDD Construction. VLSI 1999: 334-345
	1998
4		Rolf Drechsler, Nicole Drechsler, Wolfgang Günther: Fast Exact Minimization of BDDs. DAC 1998: 200-205
3		Wolfgang Günther, Rolf Drechsler: Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI 1998: 325-330
	1993
2		Stefan Geyer, Wolfgang Günther, Siegfried Paul: Erfahrungen bei objektorientierter SW-Entwicklung für ein großes Prjekt: 10 Thesen. GI Jahrestagung 1993: 433-438
1		Wolfgang Günther, Jürgen F. H. Winkler: Anwendung der Objektorientierung in einem industriellen Telekommunikationsprojekt. Informatik Spektrum 16(6): 341-348 (1993)

Coauthor Index

1	Gerhard Angst	[32] [38] [39]
2	Bernd Becker	[20] [23] [25] [31] [33] [34] [37] [40] [43] [47] [49] [50]
3	Nicole Drechsler	[4] [9] [15] [25]
4	Rolf Drechsler	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [35] [36] [37] [38] [39] [41] [42] [44] [45] [46] [48]
5	Rüdiger Ebendt	[41] [44] [45] [46] [48]
6	Thomas Eschbach	[31] [37] [38] [39] [43] [47] [49] [50]
7	Stefan Geyer	[2]
8	Andreas Hett	[34]
9	Stefan Höreth	[19] [35]
10	Dragan Jankovic	[18]
11	Lothar Linhard	[32] [38] [39]
12	Paul Molitor	[20]
13	Siegfried Paul	[2]
14	Ilia Polian	[33] [40]
15	Frank Schmiedle	[17] [30]
16	Robby Schönfeld	[20]
17	Fabio Somenzi	[27]
18	Mitchell A. Thornton (Mitchell Aaron Thornton)	[16]
19	Jürgen F. H. Winkler	[1]

Colors in the list of coauthors