| 2005 |
| 15 | EE | Muzhou Shao,
Youxin Gao,
Li-Pen Yuan,
Hung-Ming Chen,
Martin D. F. Wong:
Current Calculation on VLSI Signal Interconnects.
ISQED 2005: 580-585 |
| 14 | EE | Muzhou Shao,
Youxin Gao,
Li-Pen Yuan,
Martin D. F. Wong:
IR Drop and Ground Bounce Awareness Timing Model.
ISVLSI 2005: 226-231 |
| 2003 |
| 13 | EE | Muzhou Shao,
Martin D. F. Wong,
Huijing Cao,
Youxin Gao,
Li-Pen Yuan,
Li-Da Huang,
Seokjin Lee:
Explicit gate delay model for timing evaluation.
ISPD 2003: 32-38 |
| 12 | EE | Li-Da Huang,
Minghorng Lai,
Martin D. F. Wong,
Youxin Gao:
Maze routing with buffer insertion under transition time constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 91-95 (2003) |
| 2002 |
| 11 | EE | Li-Da Huang,
Minghorng Lai,
D. F. Wong,
Youxin Gao:
Maze Routing with Buffer Insertion under Transition Time Constraints.
DATE 2002: 702-707 |
| 10 | EE | Muzhou Shao,
D. F. Wong,
Youxin Gao,
Li-Pen Yuan,
Huijing Cao:
Shaping interconnect for uniform current density.
ICCAD 2002: 254-259 |
| 2001 |
| 9 | EE | Youxin Gao,
D. F. Wong:
A fast and accurate delay estimation method for buffered interconnects.
ASP-DAC 2001: 533-538 |
| 8 | EE | Youxin Gao,
D. F. Wong:
A graph based algorithm for optimal buffer insertion under accurate delay models.
DATE 2001: 535-539 |
| 2000 |
| 7 | EE | Youxin Gao,
D. F. Wong:
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.
DATE 2000: 512- |
| 1999 |
| 6 | EE | Youxin Gao,
D. F. Wong:
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.
ASP-DAC 1999: 217-220 |
| 5 | EE | Youxin Gao,
Martin D. F. Wong:
Wire-sizing optimization with inductance consideration using transmission-line model.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1759-1767 (1999) |
| 4 | EE | Youxin Gao,
Martin D. F. Wong:
Optimal shape function for a bidirectional wire under Elmore delay model.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 994-999 (1999) |
| 3 | EE | Youxin Gao,
D. F. Wong:
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance.
Integration 27(2): 165-178 (1999) |
| 1998 |
| 2 | EE | Youxin Gao,
D. F. Wong:
Shaping a VLSI wire to minimize delay using transmission line model.
ICCAD 1998: 611-616 |
| 1997 |
| 1 | EE | Youxin Gao,
D. F. Wong:
Optimal shape function for a bi-directional wire under Elmore delay model.
ICCAD 1997: 622-627 |