| 2008 |
|---|
| 9 | EE | Andrzej Hlawiczka,
Krzysztof Gucwa,
Tomasz Garbolino,
Michal Kopec:
Interconnect Faults Identification and Localization Using Modified Ring LFSRs.
DDECS 2008: 247-250 |
| 8 | EE | Gregor Papa,
Tomasz Garbolino,
Franc Novak:
Deterministic Test Pattern Generator Design.
EvoWorkshops 2008: 204-213 |
| 7 | EE | Tomasz Garbolino,
Gregor Papa:
Test Pattern Generator Design Optimization Based on Genetic Algorithm.
IEA/AIE 2008: 580-589 |
| 2007 |
|---|
| 6 | | Patrick Girard,
Andrzej Krasniewski,
Elena Gramatová,
Adam Pawlak,
Tomasz Garbolino:
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007
IEEE Computer Society 2007 |
| 5 | | Tomasz Garbolino,
Krzysztof Gucwa,
Michal Kopec,
Andrzej Hlawiczka:
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.
DDECS 2007: 149-152 |
| 2006 |
|---|
| 4 | | Tomasz Garbolino,
Michal Kopec,
Krzysztof Gucwa,
Andrzej Hlawiczka:
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.
DDECS 2006: 230-231 |
| 3 | EE | Michal Kopec,
Tomasz Garbolino,
Krzysztof Gucwa,
Andrzej Hlawiczka:
Test-per-Clock Detection, Localization and Identification of Interconnect Faults.
European Test Symposium 2006: 233-238 |
| 2002 |
|---|
| 2 | EE | Tomasz Garbolino,
Andrzej Hlawiczka:
Efficient test pattern generators based on specific cellular automata structures.
Microelectronics Reliability 42(6): 975-983 (2002) |
| 1999 |
|---|
| 1 | EE | Tomasz Garbolino,
Andrzej Hlawiczka:
A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.
EDCC 1999: 321-338 |
