 | 2009 |
|---|
| 11 |       | Mario García-Valderas,
Luis Entrena,
Raúl Fernández Cardenal,
Celia López-Ongil,
Marta Portela-García:
SET Emulation Under a Quantized Delay Model.
J. Electronic Testing 25(1): 107-116 (2009) |
| 2007 |
|---|
| 10 | | Mario García-Valderas,
Raúl Fernández Cardenal,
Celia López-Ongil,
Marta Portela-García,
Luis Entrena:
SET Emulation Under a Quantized Delay Model.
DFT 2007: 68-77 |
| 9 | | Marta Portela-García,
Celia López-Ongil,
Mario García-Valderas,
Luis Entrena:
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.
IOLTS 2007: 101-106 |
| 8 | | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
CoRR abs/0710.4757: (2007) |
| 2006 |
|---|
| 7 |  | Mario García-Valderas,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena-Arrontes:
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.
DDECS 2006: 218-219 |
| 6 | | Mario García-Valderas,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena:
Emulation-based Fault Injection in Circuits with Embedded Memories.
IOLTS 2006: 183-184 |
| 2005 |
|---|
| 5 | | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation.
DATE 2005: 308-309 |
| 4 | | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation.
FPL 2005: 397-402 |
| 3 | | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.
IOLTS 2005: 43-48 |
| 2004 |
|---|
| 2 | | Michael G. Lorenz,
Luis Mengibar,
Mario García-Valderas,
Luis Entrena:
Power Consumption Reduction Through Dynamic Reconfiguration.
FPL 2004: 751-760 |
| 1 | | Mario García-Valderas,
Celia López-Ongil,
Marta Portela-García,
Luis Entrena:
Transient Fault Emulation of Hardened Circuits in FPGA Platforms.
IOLTS 2004: 109-114 |
