| 2008 | ||
|---|---|---|
| 5 | EE | Akhil Garg, Prashant Dubey: On Chip Jitter Measurement through a High Accuracy TDC. ISQED 2008: 844-847 |
| 2007 | ||
| 4 | Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Built in Defect Prognosis for Embedded Memories. DDECS 2007: 167-172 | |
| 3 | EE | Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: GALS Based Shared Test Architecture for Embedded Memories. ISCAS 2007: 157-160 |
| 2 | EE | Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani: Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI 2007: 171-178 |
| 2006 | ||
| 1 | EE | Akhil Garg, Prashant Dubey: Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT 2006: 166-174 |
| 1 | Sravan Kumar Bhaskarani | [2] [3] [4] |
| 2 | Prashant Dubey | [1] [2] [3] [4] [5] |