| 2008 |
| 13 | EE | Arunprasad Venkatraman,
Rajesh Garg,
Sunil P. Khatri:
A robust, fast pulsed flip-flop design.
ACM Great Lakes Symposium on VLSI 2008: 119-122 |
| 12 | EE | Suganth Paul,
Rajesh Garg,
Sunil P. Khatri:
Pipelined network of PLA based circuit design.
ACM Great Lakes Symposium on VLSI 2008: 213-218 |
| 11 | EE | Salman Gopalani,
Rajesh Garg,
Sunil P. Khatri,
Mosong Cheng:
A lithography-friendly structured ASIC design approach.
ACM Great Lakes Symposium on VLSI 2008: 315-320 |
| 10 | EE | Rajesh Garg,
Charu Nagpal,
Sunil P. Khatri:
A fast, analytical estimator for the SEU-induced pulse width in combinational designs.
DAC 2008: 918-923 |
| 9 | EE | Charu Nagpal,
Rajesh Garg,
Sunil P. Khatri:
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.
DATE 2008: 354-359 |
| 8 | EE | Rajesh Garg,
Gagandeep Mallarapu,
Sunil P. Khatri:
A Single-supply True Voltage Level Shifter.
DATE 2008: 979-984 |
| 2007 |
| 7 | EE | Jeff Cobb,
Rajesh Garg,
Sunil P. Khatri:
A methodology for interconnect dimension determination.
ISPD 2007: 189-195 |
| 2006 |
| 6 | EE | Rajesh Garg,
Mario Sanchez,
Kanupriya Gulati,
Nikhil Jayakumar,
Anshul Gupta,
Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs.
ACM Great Lakes Symposium on VLSI 2006: 217-222 |
| 5 | EE | Nikhil Jayakumar,
Rajesh Garg,
Bruce Gamache,
Sunil P. Khatri:
A PLA based asynchronous micropipelining approach for subthreshold circuit design.
DAC 2006: 419-424 |
| 4 | EE | Rajesh Garg,
Nikhil Jayakumar,
Sunil P. Khatri,
Gwan Choi:
A design approach for radiation-hard digital electronics.
DAC 2006: 773-778 |
| 3 | EE | Eric Menendez,
Dumezie Maduike,
Rajesh Garg,
Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications.
ICCD 2006 |
| 2 | EE | Rajesh Garg,
Nikhil Jayakumar,
Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis.
ICCD 2006 |
| 1 | EE | Rajesh Garg,
Sunil P. Khatri:
Generalized buffering of PTL logic stages using Boolean division.
ISCAS 2006 |