Rajesh Garg

	2009
19		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
18		Rajesh Garg, Sunil P. Khatri: Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC 2009: 461-467
17		Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya: Design and implementation of a sub-threshold BFSK transmitter. ISQED 2009: 664-672
16		Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi: SEU hardened clock regeneration circuits. ISQED 2009: 806-813
	2008
15		Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri: A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI 2008: 119-122
14		Suganth Paul, Rajesh Garg, Sunil P. Khatri: Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI 2008: 213-218
13		Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng: A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI 2008: 315-320
12		Rajesh Garg, Charu Nagpal, Sunil P. Khatri: A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC 2008: 918-923
11		Charu Nagpal, Rajesh Garg, Sunil P. Khatri: A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE 2008: 354-359
10		Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri: A Single-supply True Voltage Level Shifter. DATE 2008: 979-984
9		Rajesh Garg, Sunil P. Khatri: A novel, highly SEU tolerant digital circuit design approach. ICCD 2008: 14-20
8		Rajesh Garg, Peng Li, Sunil P. Khatri: Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS 2008: 1788-1791
	2007
7		Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri: A methodology for interconnect dimension determination. ISPD 2007: 189-195
	2006
6		Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
5		Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri: A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC 2006: 419-424
4		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi: A design approach for radiation-hard digital electronics. DAC 2006: 773-778
3		Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri: CMOS Comparators for High-Speed and Low-Power Applications. ICCD 2006
2		Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri: On the Improvement of Statistical Static Timing Analysis. ICCD 2006
1		Rajesh Garg, Sunil P. Khatri: Generalized buffering of PTL logic stages using Boolean division. ISCAS 2006

Coauthor Index

1	Kalyana C. Bollapalli	[19]
2	Mosong Cheng	[13]
3	Gwan S. Choi (Gwan Choi)	[4] [16]
4	Jeff L. Cobb	[7]
5	Rajballav Dash	[16]
6	Bruce Gamache	[5]
7	Salman Gopalani	[13]
8	Kanupriya Gulati	[6] [19]
9	Anshul Gupta	[6]
10	Nikhil Jayakumar	[2] [4] [5] [6]
11	Sunil P. Khatri	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
12	Peng Li	[8]
13	Dumezie Maduike	[3]
14	Gagandeep Mallarapu	[10]
15	Eric Menendez	[3]
16	Charu Nagpal	[11] [12]
17	Suganth Paul	[14] [17]
18	Mario Sanchez	[6]
19	Sheila Vaidya	[17]
20	Arunprasad Venkatraman	[15]