 | 2009 |
|---|
| 12 |       | Benaoumeur Senouci,
Mourad Bouache,
Bernard Goossens:
Heterogeneous Multi-processor SoC Design: Hardware Bridging and Exploration Methodology.
ESA 2009: 204-210 |
| 2006 |
|---|
| 11 |  | Bernard Goossens,
David Defour:
Ordonnancement distribué d'instructions.
Technique et Science Informatiques 25(7): 827-844 (2006) |
| 2005 |
|---|
| 10 | | Bernard Goossens,
David Defour:
The instruction register file micro-architecture.
Future Generation Comp. Syst. 21(4): 767-773 (2005) |
| 2003 |
|---|
| 9 | | Bernard Goossens:
The Instruction Register File.
PaCT 2003: 467-481 |
| 2002 |
|---|
| 8 | | Bernard Goossens:
Typing the ISA to cluster the processor.
Future Generation Comp. Syst. 18(6): 789-796 (2002) |
| 2001 |
|---|
| 7 | | Bernard Goossens:
Typing the ISA to Cluster the Processor.
PaCT 2001: 232-242 |
| 6 | | Bernard Goossens:
Handling 16 instructions per cycle in a superscalar processor.
Future Generation Comp. Syst. 17(6): 699-709 (2001) |
| 1999 |
|---|
| 5 | | Bernard Goossens,
Hassane Essafi,
Marc Pic:
Hardware and Software Optimizations for Multimedia Databases.
PaCT 1999: 365-370 |
| 1997 |
|---|
| 4 | | Bernard Goossens:
A Multithreaded Vector Co-processor.
PaCT 1997: 311-321 |
| 1996 |
|---|
| 3 | | Bernard Goossens,
Duc Thang Vu:
On-Chip Multiprocessing.
Euro-Par, Vol. II 1996: 789-796 |
| 2 | | Bernard Goossens,
Duc Thang Vu:
Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.
ISPAN 1996: 36-42 |
| 1995 |
|---|
| 1 | | Bernard Goossens,
Duc Thang Vu:
Further Pipelining and Multithreading to Improve RISC Processor Speed. A Proposed Architecture and Simulation Results.
PaCT 1995: 326-340 |
