Kees Goossens
List of publications from the DBLP Bibliography Server - FAQ
| 2009 | ||
|---|---|---|
| 44 | Andreas Hansson, Kees Goossens: An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. CODES+ISSS 2009: 99-108 | |
| 43 | Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad: A high-level debug environment for communication-centric debug. DATE 2009: 202-207 | |
| 42 | Andreas Hansson, Mahesh Subburaman, Kees Goossens: Aelite: A flit-synchronous Network on Chip with composable and predictable services. DATE 2009: 250-255 | |
| 41 | Muhammad Aqeel Wahlah, Kees G. W. Goossens: Modeling reconfiguration in a FPGA with a hardwired network on chip. IPDPS 2009: 1-8 | |
| 40 | Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken: CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) | |
| 2008 | ||
| 39 | Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin: You can catch more bugs with transaction level honey. CODES+ISSS 2008: 121-124 | |
| 38 | Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij: Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. NOCS 2008: 211-212 | |
| 37 | Bart Vermeulen, Kees Goossens, Siddharth Umrani: Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. NOCS 2008: 3-12 | |
| 36 | Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah: Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. NOCS 2008: 45-54 | |
| 35 | Benny Akesson, Liesbeth Steffens, Eelke Strooisma, Kees G. W. Goossens: Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration. RTCSA 2008: 3-14 | |
| 34 | Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten: A monitoring-aware network-on-chip design flow. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 397-410 (2008) | |
| 2007 | ||
| 33 | Andreas Hansson, Martijn Coenen, Kees Goossens: Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. CODES+ISSS 2007: 149-154 | |
| 32 | Benny Akesson, Kees Goossens, Markus Ringhofer: Predator: a predictable SDRAM memory controller. CODES+ISSS 2007: 251-256 | |
| 31 | Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten: Congestion-controlled best-effort communication for networks-on-chip. DATE 2007: 948-953 | |
| 30 | Andreas Hansson, Martijn Coenen, Kees Goossens: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. DATE 2007: 954-959 | |
| 29 | Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek: Communication-Centric SoC Debug Using Transactions. European Test Symposium 2007: 69-76 | |
| 28 | Andreas Hansson, Kees Goossens: Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. NOCS 2007: 233-242 | |
| 27 | Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek: Transaction-Based Communication-Centric Debug. NOCS 2007: 95-106 | |
| 2006 | ||
| 26 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: Mapping and configuration methods for multi-use-case networks on chips. ASP-DAC 2006: 146-151 | |
| 25 | Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. CODES+ISSS 2006: 130-135 | |
| 24 | Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A methodology for mapping multiple use-cases onto networks on chips. DATE 2006: 118-123 | |
| 23 | Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis: Networks on chips for high-end consumer-electronics TV system architectures. DATE Designers' Forum 2006: 148-153 | |
| 22 | Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten: A Monitoring-Aware Network-on-Chip Design Flow. DSD 2006: 97-106 | |
| 21 | Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes: Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. European Test Symposium 2006: 213-218 | |
| 20 | Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten: NoC monitoring: impact on the design flow. ISCAS 2006 | |
| 19 | Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen: Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. VLSI-SoC 2006: 80-85 | |
| 2005 | ||
| 18 | Kees Goossens: Formal Methods for Networks on Chips. ACSD 2005: 188-189 | |
| 17 | Biniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu: Deadlock Prevention in the Æthereal Protocol. CHARME 2005: 345-348 | |
| 16 | Andreas Hansson, Kees Goossens, Andrei Radulescu: A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS 2005: 75-80 | |
| 15 | Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. DATE 2005: 1182-1187 | |
| 14 | Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen: An event-based monitoring service for networks on chip. ACM Trans. Design Autom. Electr. Syst. 10(4): 702-723 (2005) | |
| 13 | Kees Goossens, John Dielissen, Andrei Radulescu: Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design & Test of Computers 22(5): 414-421 (2005) | |
| 12 | Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 4-17 (2005) | |
| 2004 | ||
| 11 | Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. DATE 2004: 764-769 | |
| 10 | Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. DATE 2004: 878-883 | |
| 2003 | ||
| 9 | Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355 | |
| 2002 | ||
| 8 | Kees G. W. Goossens, Om Prakash Gangwal: The Cost of Communication Protocols and Coordination Languages in Embedded Systems. COORDINATION 2002: 174-190 | |
| 7 | Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen: Networks on Silicon: Combining Best-Effort and Guaranteed Services. DATE 2002: 423-427 | |
| 6 | Paul Wielage, Kees G. W. Goossens: Networks on Silicon: Blessing or Nightmare? DSD 2002: 196-200 | |
| 2001 | ||
| 5 | Kees G. W. Goossens: A protocol and memory manager for on-chip communication. ISCAS (2) 2001: 225-228 | |
| 1998 | ||
| 4 | Rafael Peset Llopis, Kees G. W. Goossens: The petrol approach to high-level power estimation. ISLPED 1998: 130-132 | |
| 1995 | ||
| 3 | Kees G. W. Goossens: Reasoning about VHDL using operational and observational semantics. CHARME 1995: 311-327 | |
| 1993 | ||
| 2 | Kees G. W. Goossens: Stucture and Behaviour in Hardware Verification. HUG 1993: 75-88 | |
| 1992 | ||
| 1 | Kees G. W. Goossens: Operational Semantics Based on Formal Symbolic Simulation. TPHOLs 1992: 487-506 | |