 | 2009 |
|---|
| 8 |       | Kristofer Vorwerk,
Andrew A. Kennings,
Jonathan W. Greene:
Improving Simulated Annealing-Based FPGA Placement With Directed Moves.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 179-192 (2009) |
| 2007 |
|---|
| 7 | | Kristofer Vorwerk,
Andrew A. Kennings,
Jonathan W. Greene,
Doris T. Chen:
Improving Annealing Via Directed Moves.
FPL 2007: 363-370 |
| 6 | | Wenyi Feng,
Jonathan W. Greene:
Post-Placement Interconnect Entropy.
IEEE Trans. VLSI Syst. 15(8): 945-948 (2007) |
| 2006 |
|---|
| 5 | | Wenyi Feng,
Jonathan W. Greene:
Post-placement interconnect entropy.
FPGA 2006: 227 |
| 4 | | Wenyi Feng,
Jonathan W. Greene:
Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?
SLIP 2006: 41-48 |
| 1993 |
|---|
| 3 | | Vwani P. Roychowdhury,
Jonathan W. Greene,
Abbas El Gamal:
Segmented channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 79-95 (1993) |
| 1990 |
|---|
| 2 | | Jonathan W. Greene,
Vwani P. Roychowdhury,
Sinan Kaptanoglu,
Abbas El Gamal:
Segmented Channel Routing.
DAC 1990: 567-572 |
| 1984 |
|---|
| 1 | | Jonathan W. Greene,
Abbas El Gamal:
Configuration of VLSI Arrays in the Presence of Defects.
J. ACM 31(4): 694-717 (1984) |
