Mark R. Greenstreet

	2012
53		Brad D. Bingham, Mark R. Greenstreet: Modeling Energy-Time Trade-Offs in VLSI Computation. IEEE Trans. Computers 61(4): 530-547 (2012)
	2011
52		Suwen Yang, Ian W. Jones, Mark R. Greenstreet: Synchronizer Performance in Deep Sub-Micron Technology. ASYNC 2011: 33-42
51		Vijay Anand Korthikanti, Gul Agha, Mark R. Greenstreet: On the Energy Complexity of Parallel Algorithms. ICPP 2011: 562-570
	2010
50		Chao Yan, Mark R. Greenstreet, Jochen Eisinger: Formal Verification of an Arbiter Circuit. ASYNC 2010: 165-175
49		Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony: Varactor-based signal restoration for near-speed-of-light surfing global interconnect. CICC 2010: 1-4
	2009
48		Mark R. Greenstreet: Verifying VLSI Circuits. ATVA 2009: 1-20
47		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52
46		Tarik Ono-Tesfaye, Mark R. Greenstreet: A modular synchronizing FIFO for NoCs. NOCS 2009: 224-233
45		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS 2009: 234-243
	2008
44		Mark R. Greenstreet, Suwen Yang: Verifying start-up conditions for a ring oscillator. ACM Great Lakes Symposium on VLSI 2008: 201-206
43		Chao Yan, Mark R. Greenstreet: Faster projection based methods for circuit level verification. ASP-DAC 2008: 410-415
42		Chao Yan, Mark R. Greenstreet: Verifying an Arbiter Circuit. FMCAD 2008: 1-9
41		Brad D. Bingham, Mark R. Greenstreet: Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds. ISPA 2008: 143-152
40		Brad D. Bingham, Mark R. Greenstreet: Energy Optimal Scheduling on Multiprocessors with Migration. ISPA 2008: 153-161
39		Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Practical Asynchronous Interconnect Network Design. IEEE Trans. VLSI Syst. 16(5): 579-588 (2008)
	2007
38		Suwen Yang, Mark R. Greenstreet, Jihong Ren: A Jitter Attenuating Timing Chain. ASYNC 2007: 25-38
37		Suwen Yang, Mark R. Greenstreet: Simulating Improbable Events. DAC 2007: 154-157
36		Suwen Yang, Mark R. Greenstreet: Computing synchronizer failure probabilities. DATE 2007: 1361-1366
35		Chao Yan, Mark R. Greenstreet: Circuit Level Verification of a High-Speed Toggle. FMCAD 2007: 199-206
34		Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux: A Survey and Taxonomy of GALS Design Styles. IEEE Design & Test of Computers 24(5): 418-428 (2007)
	2006
33		Mark R. Greenstreet, Jihong Ren: Surfing Interconnect. ASYNC 2006: 98-106
32		Suwen Yang, Mark R. Greenstreet: Analysing the Robustness of Surfing Circuits. Electr. Notes Theor. Comput. Sci. 153(3): 65-77 (2006)
	2005
31		Suwen Yang, Brian D. Winters, Mark R. Greenstreet: Energy Efficient Surfing. ASYNC 2005: 2-11
30		Jihong Ren, Mark R. Greenstreet: A unified optimization framework for equalization filter synthesis. DAC 2005: 638-643
29		Suwen Yang, Mark R. Greenstreet: Noise margin analysis for dynamic logic circuits. ICCAD 2005: 406-412
28		Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274
	2004
27		Jihong Ren, Mark R. Greenstreet: A Signal Integrity Test Bed for PCB Buses. ICCD 2004: 132-137
26		Jihong Ren, Mark R. Greenstreet: Crosstalk Cancellation for Realistic PCB Buses. PATMOS 2004: 48-57
	2003
25		Ajanta Chakraborty, Mark R. Greenstreet: Efficient Self-Timed Interfaces for Crossing Clock Domains. ASYNC 2003: 78-88
24		Jihong Ren, Mark R. Greenstreet: Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. DAC 2003: 592-597
23		Jihong Ren, Mark R. Greenstreet: Equalizing Filter Design for Crosstalk Cancellation. ISVLSI 2003: 272-274
22		Brian D. Winters, Mark R. Greenstreet: Surfing: a robust form of wave pipelining using self-timed circuit techniques. Microprocessors and Microsystems 27(9): 409-419 (2003)
	2002
21		Claire Tomlin, Mark R. Greenstreet: Hybrid Systems: Computation and Control, 5th International Workshop, HSCC 2002, Stanford, CA, USA, March 25-27, 2002, Proceedings Springer 2002
20		Mark R. Greenstreet, Brian D. Winters: A Negative-Overhead, Self-Timed Pipeline. ASYNC 2002: 37-46
19		Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier: An Event Spacing Experiment. ASYNC 2002: 47-56
	2001
18		Mark R. Greenstreet, Brian de Alwis: How to Achieve Worst-Case Performance. ASYNC 2001: 206-
17		Anthony Winstanley, Mark R. Greenstreet: Temporal Properties of Self-Timed Rings. CHARME 2001: 140-154
16		Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet: A light-weight framework for hardware verification. STTT 3(3): 286-313 (2001)
	1999
15		Mark R. Greenstreet, Tarik Ono-Tesfaye: A Fast, asP*, RGD Arbiter. ASYNC 1999: 173-185
14		Mark R. Greenstreet: Real-Time Merging. ASYNC 1999: 186-
13		Mark R. Greenstreet, Ian Mitchell: Reachability Analysis Using Polygonal Projections. HSCC 1999: 103-116
12		Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet: A Light-Weight Framework for Hardware Verification. TACAS 1999: 330-344
11		Christoph Kern, Mark R. Greenstreet: Formal verification in hardware design: a survey. ACM Trans. Design Autom. Electr. Syst. 4(2): 123-193 (1999)
	1998
10		Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet: Verifying a Self-Timed Divider. ASYNC 1998: 146-158
9		Mark R. Greenstreet, Ian Mitchell: Integrating Projections. HSCC 1998: 159-174
	1997
8		Peggy B. K. Pang, Mark R. Greenstreet: Self-Timed Meshes Are Faster Than Synchronous. ASYNC 1997: 30-
	1996
7		Mark R. Greenstreet: Verifying Safety Properties of Differential Equations. CAV 1996: 277-287
	1995
6		Mark R. Greenstreet: Implementing a STARI chip. ICCD 1995: 38-43
5		Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Asynchronous Circuits. IEEE Design & Test of Computers 12(1): 24-31 (1995)
	1994
4		Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Refinement. ICCD 1994: 225-229
	1992
3		Mark R. Greenstreet: Using Synchronized Transitions for Simulation and Timing Verification. Designing Correct Circuits 1992: 215-236
	1990
2		Mark R. Greenstreet, Kenneth Steiglitz: Bubbles can make self-timed pipelines fast. VLSI Signal Processing 2(3): 139-148 (1990)
	1988
1		Jørgen Staunstrup, Mark R. Greenstreet: From High-Level Descriptions to VLSI Circuits. BIT 28(3): 620-638 (1988)

Coauthor Index

1	Gul A. Agha (Gul Agha)	[51]
2	Brian de Alwis	[18]
3	Brad D. Bingham	[40] [41] [53]
4	Ajanta Chakraborty	[25]
5	Robert J. Drost	[49]
6	Jochen Eisinger	[50]
7	Aurélien Garivier	[19]
8	Ian W. Jones	[52]
9	Christoph Kern	[10] [11] [12] [16]
10	Vijay Anand Korthikanti (Vijay Anand Reddy)	[51]
11	Trevor Wing Sang Lee	[4] [5]
12	Guy Lemieux (Guy G. Lemieux, Guy G. F. Lemieux)	[34] [45] [47]
13	Shahriar Mirabbasi	[49]
14	Ian M. Mitchell (Ian Mitchell)	[9] [13]
15	Frank O'Mahony	[49]
16	Tarik Ono-Tesfaye	[10] [12] [15] [16] [46]
17	Peggy B. K. Pang	[8]
18	Bradley R. Quinton	[28] [39]
19	Jihong Ren	[23] [24] [26] [27] [30] [33] [38]
20	Carl-Johan H. Seger	[4] [5]
21	Jørgen Staunstrup	[1]
22	Kenneth Steiglitz	[2]
23	Paul Teehan	[34] [45] [47]
24	Claire J. Tomlin (Claire Tomlin)	[21]
25	Steven J. E. Wilton	[28] [39]
26	Anthony Winstanley	[17] [19]
27	Brian D. Winters	[20] [22] [31]
28	Chao Yan	[35] [42] [43] [50]
29	Suwen Yang	[29] [31] [32] [36] [37] [38] [44] [49] [52]

Colors in the list of coauthors

Last update Fri May 25 01:42:58 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page