 | 2009 |
| 20 |  | Bharathram Sivasubramanian,
Warren J. Gross,
Harry Leib:
Design and FPGA implementation of iterative decoders for codes on graphs.
CCECE 2009: 1080-1084 |
| 2008 |
| 19 |  | Andrew J. Wong,
Warren J. Gross:
Configurable Flow Models for FPGA Particle Graphics Engines.
FCCM 2008: 283-284 |
| 18 |  | Yousef El-Kurdi,
David Fernández,
Evgueni Souleimanov,
Dennis Giannacopoulos,
Warren J. Gross:
FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method.
Computer Physics Communications 178(8): 558-570 (2008) |
| 17 |  | Shaoqiang Bi,
Warren J. Gross:
The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison.
IEEE Trans. Computers 57(12): 1624-1632 (2008) |
| 16 |  | Saeed Sharifi Tehrani,
Shie Mannor,
Warren J. Gross:
Fully Parallel Stochastic LDPC Decoders.
IEEE Transactions on Signal Processing 56(11): 5692-5703 (2008) |
| 15 |  | Saeed Sharifi Tehrani,
Christophe Jégo,
Bo Zhu,
Warren J. Gross:
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices.
IEEE Transactions on Signal Processing 56(11): 5733-5739 (2008) |
| 14 |  | John Sachs Beeckler,
Warren J. Gross:
Particle graphics on reconfigurable hardware.
TRETS 1(3): (2008) |
| 2007 |
| 13 |  | Jahyun J. Koo,
David Fernández,
Ashraf Haddad,
Warren J. Gross:
Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers.
ASAP 2007: 30-35 |
| 12 |  | Jahyun J. Koo,
Alan Evans,
Warren J. Gross:
Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer.
FPL 2007: 11-16 |
| 11 |  | Saeed Sharifi Tehrani,
Shie Mannor,
Warren J. Gross:
Survey of Stochastic Computation on Factor Graphs.
ISMVL 2007: 54 |
| 10 |  | Laurier Boulianne,
Michel Dumontier,
Warren J. Gross:
A stochastic particle-based biological system simulator.
SCSC 2007: 794-801 |
| 9 |  | Saeed Sharifi Tehrani,
Shie Mannor,
Warren J. Gross:
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding.
SiPS 2007: 255-260 |
| 8 |  | Warren J. Gross,
Frank R. Kschischang,
P. Glenn Gulak:
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
IEEE Trans. VLSI Syst. 15(3): 309-318 (2007) |
| 2006 |
| 7 |  | Yousef El-Kurdi,
Warren J. Gross,
Dennis Giannacopoulos:
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs.
FCCM 2006: 293-294 |
| 6 |  | Warren J. Gross,
Frank R. Kschischang,
Ralf Koetter,
P. Glenn Gulak:
Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Transactions on Communications 54(6): 1143 (2006) |
| 5 |  | Warren J. Gross,
Frank R. Kschischang,
Ralf Koetter,
P. Glenn Gulak:
Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes.
IEEE Transactions on Communications 54(7): 1224-1234 (2006) |
| 2005 |
| 4 |  | John Sachs Beeckler,
Warren J. Gross:
FPGA Particle Graphics Hardware.
FCCM 2005: 85-94 |
| 3 |  | Shaoqiang Bi,
Warren J. Gross,
Wei Wang,
Asim J. Al-Khalili,
M. N. S. Swamy:
An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.
IWSOC 2005: 396-399 |
| 2 |  | Warren J. Gross,
Frank R. Kschischang,
Ralf Koetter,
P. Glenn Gulak:
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.
VLSI Signal Processing 39(1-2): 93-111 (2005) |
| 2004 |
| 1 |  | Warren J. Gross,
Frank R. Kschischang,
P. Glenn Gulak:
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
FCCM 2004: 310-311 |