| 2008 |
|---|
| 9 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Shianling Wu,
Zhigang Wang,
Zhigang Jiang,
Boryau Sheu,
Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers 25(2): 122-130 (2008) |
| 2004 |
|---|
| 8 | EE | Heon C. Kim,
Hong Shin Jun,
Xinli Gu,
Sung Soo Chung:
At-Speed Interconnect Test and Diagnosis of External Memories on a System.
ITC 2004: 156-162 |
| 7 | EE | Xinli Gu,
Cyndee Wang,
Abby Lee,
Bill Eklow,
Kun-Han Tsai,
Jan Arild Tofte,
Mark Kassab,
Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage.
ITC 2004: 525-533 |
| 2002 |
|---|
| 6 | EE | Xinli Gu,
Weili Wang,
Kevin Li,
Heon C. Kim,
Sung Soo Chung:
Re-Using DFT Logic for Functional and Silicon Debugging Test.
ITC 2002: 648-656 |
| 2001 |
|---|
| 5 | | Xinli Gu,
Sung Soo Chung,
Frank Tsang,
Jan Arild Tofte,
Hamid Rahmanian:
An effort-minimized logic BIST implementation method.
ITC 2001: 1002-1010 |
| 1998 |
|---|
| 4 | EE | Mokhtar Hirech,
James Beausang,
Xinli Gu:
A new approach to scan chain reordering using physical design information.
ITC 1998: 348- |
| 1995 |
|---|
| 3 | | Xinli Gu,
Krzysztof Kuchcinski,
Zebo Peng:
An Efficient and Economic Partitioning Approach for Testability.
ITC 1995: 403-412 |
| 2 | EE | Xinli Gu:
RT level testability-driven partitioning.
VTS 1995: 176-183 |
| 1994 |
|---|
| 1 | EE | Xinli Gu,
Krzysztof Kuchcinski,
Zebo Peng:
Testability analysis and improvement from VHDL behavioral specifications.
EURO-DAC 1994: 644-649 |
