Kanupriya Gulati

	2009
21		Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri: Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362
20		Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444
19		Kanupriya Gulati, Sunil P. Khatri: Accelerating statistical static timing analysis using graphics processing units. ASP-DAC 2009: 260-265
18		Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry: Fast circuit simulation on graphics processing units. ASP-DAC 2009: 403-408
17		Kanupriya Gulati, Sunil P. Khatri, Peng Li: Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287
16		Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
	2008
15		Kanupriya Gulati, Sunil P. Khatri: Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150
14		Kanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827
13		Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
12		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008)
	2007
11		Eugene Goldberg, Kanupriya Gulati: On Complexity of Internal and External Equivalence Checking. DSD 2007: 197-206
10		Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279
9		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790
	2006
8		Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222
7		Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri: Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855
6		Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson: Network coding for routability improvement in VLSI. ICCAD 2006: 820-823
5		Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi: An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006
4		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006
3		Kanupriya Gulati, M. Lovell, Sunil P. Khatri: Efficient don't care computation for hierarchical designs. ISCAS 2006
2		Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri: Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006
	2005
1		Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114

Coauthor Index

1	Kalyana C. Bollapalli	[20]
2	Jeff L. Cobb	[21]
3	John F. Croix	[18]
4	Chunjie Duan	[2]
5	Rajesh Garg	[8] [20]
6	Eugene Goldberg (Evguenii I. Goldberg)	[10] [11]
7	Anshul Gupta	[8]
8	Abhijit Jas	[16]
9	Nikhil Jayakumar	[1] [4] [6] [8] [9] [12]
10	Sunil P. Khatri	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
11	Brock J. LaMeres	[7]
12	Peng Li	[17]
13	M. Lovell	[3]
14	Srinivas Patil	[16]
15	Suganth Paul	[16]
16	Nikhil Saluja	[13]
17	Mario Sanchez	[8]
18	Rahm Shastry	[18]
19	Weiping Shi	[5]
20	Alexander Sprintson	[6]
21	Mandar Waghmode	[5]
22	D. M. H. Walker (Duncan M. Hank Walker)	[12]